Electrostatic discharge protection semiconductor device

Abstract

An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

What is claimed is: 
     
       1. An electrostatic discharge (ESD) protection semiconductor device comprising:
 a substrate; 
 a gate set formed on the substrate; 
 a source region and a drain region formed in the substrate respectively at two sides of the gate set, and the source region and the drain region comprising a first conductivity type, wherein the drain region is electrically connected to an input/out (I/O) pad; 
 at least a first doped region formed in the drain region; the first doped region comprising a second conductivity type complementary to the first conductivity type, and the first doped region being electrically connected to a ground potential, wherein the gate set is disposed in between the source region and the first doped region; and 
 a first blocking structure surrounding the first doped region and isolating the first doped region from the drain region. 
 
     
     
       2. The ESD protection semiconductor device according to  claim 1 , wherein the first blocking structure comprises shallow trench isolation (STI), dummy gate, or salicide blocking (SAB) layer. 
     
     
       3. The ESD protection semiconductor device according to  claim 2 , wherein the first blocking structure comprises a STI-dummy gate mixed blocking structure or a STI-SAB mixed blocking structure. 
     
     
       4. The ESD protection semiconductor device according to  claim 1 , further comprising a second doped region formed in the source region, and the second doped region comprising the second conductivity type. 
     
     
       5. The ESD protection semiconductor device according to  claim 4 , further comprising a second blocking structure surrounding the second doped region and isolating the second doped region from the source region. 
     
     
       6. The ESD protection semiconductor device according to  claim 5 , wherein the second blocking structure comprises STI, dummy gate, or SAB layer. 
     
     
       7. The ESD protection semiconductor device according to  claim 1 , wherein the gate set comprises a single gate structure, the single gate structure and the source region are electrically connected to a ground potential, and the drain region is electrically connected to an input/output (I/O) pad. 
     
     
       8. The ESD protection semiconductor device according to  claim 1 , wherein the gate set comprises:
 a third doped region comprising the first conductivity type; 
 a first gate structure positioned on the substrate and between the third doped region and the drain region; and 
 a second gate structure positioned on the substrate and between the third doped region and the source region. 
 
     
     
       9. The ESD protection semiconductor device according to  claim 8 , wherein the first gate structure and the second gate structure are physically spaced apart from each other by the third doped region, and the first gate structure and the second gate structure are electrically connected to each other by the third doped region. 
     
     
       10. The ESD protection semiconductor device according to  claim 1 , further comprising:
 a first well region formed in the substrate, the first well region comprising the first conductivity type; and 
 a second well region formed in the substrate, the second well region comprising the second conductivity type, 
 wherein the first well region and the second well region are spaced apart from each other by the substrate. 
 
     
     
       11. The ESD protection semiconductor device according to  claim 10 , wherein the drain region and the first doped region are formed in the first well region, and the source region is formed in the second well region. 
     
     
       12. The ESD protection semiconductor device according to  claim 10 , further comprising a second doped region formed in the source region in the second well region, and the second doped region comprising the second conductivity type. 
     
     
       13. The ESD protection semiconductor device according to  claim 1 , wherein the source region comprises a plurality of source fins parallel with each other, and the drain region comprises a plurality of drain fins parallel with each other. 
     
     
       14. The ESD protection semiconductor device according to  claim 13 , wherein the first doped region further comprises at least a first doped fin, and the first doped fin is parallel with the drain fins and physically spaced apart from the drain fins.