Shallow trench isolation trenches and methods for NAND memory

Abstract

A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and isotropically etching the exposed portion of the surface of the second dielectric material to form an air gap in the shallow trench isolation trench.

The invention claimed is: 
     
       1. A method of forming a shallow trench isolation trench in a semiconductor substrate, the method comprising:
 forming a trench in a region of the substrate; 
 forming a liner in the trench, wherein the liner comprises a first dielectric material; 
 adhering a halogen element to the liner; 
 forming a second dielectric material in the trench; 
 annealing the first dielectric material and the second dielectric material; 
 forming a conductive layer over the second dielectric material; 
 etching to form etched rows of conductive material and expose the second dielectric material between the etched rows of conductive material; and 
 isotropically etching the exposed second dielectric material to remove second dielectric material under the etched rows of conductive material to form air gaps in the shallow trench isolation trench. 
 
     
     
       2. The method of  claim 1 , wherein the halogen element comprises one or more of fluorine, chlorine, bromine, iodine, and astatine. 
     
     
       3. The method of  claim 1 , wherein the region comprises an n-well or a p-well. 
     
     
       4. The method of  claim 1 , wherein the region comprises an active area region of the substrate. 
     
     
       5. The method of  claim 1 , wherein the first dielectric material comprises one or more of silicon dioxide, silicon nitride, silicon oxynitride, and a low K dielectric. 
     
     
       6. The method of  claim 1 , wherein adhering comprises generating a fluorine plasma. 
     
     
       7. The method of  claim 1 , wherein adhering comprises adhering fluorine to a surface of the liner. 
     
     
       8. The method of  claim 1 , wherein the second dielectric material comprises one or more of a polysilazane, a spin-on-glass (SOG) polymer, methyl silsesquioxane (MSQ), and hydrogen silsesquioxane (HSQ). 
     
     
       9. The method of  claim 1 , wherein forming the second dielectric material comprises depositing a polysilazane at room temperature, followed by a baking treatment between about 100° C. to about 350° C. 
     
     
       10. The method of  claim 1 , wherein isotropically etching comprises using one or more of (a) vapor phase cleaning using hydrofluoric acid, and (b) wet etching using hydrofluoric acid. 
     
     
       11. A method of forming an air gap in a semiconductor substrate, the method comprising:
 forming a trench in an active area region of a substrate; 
 forming a silicon dioxide liner in the trench; 
 adhering a halogen element to a surface of the silicon dioxide liner; 
 forming a polysilazane material in the trench; 
 increasing a porosity of the polysilazane material; 
 forming a conductive layer over the polysilazane material; 
 etching to form etched rows of conductive material and expose the polysilazane material between the etched rows of conductive material; and 
 isotropically etching the exposed polysilazane material to remove second dielectric material under the etched rows of conductive material to form air gaps in the shallow trench isolation trench. 
 
     
     
       12. The method of  claim 11 , wherein the halogen element comprises one or more of fluorine, chlorine, bromine, iodine, and astatine. 
     
     
       13. The method of  claim 11 , wherein the active area region comprises an n-well or a p-well. 
     
     
       14. The method of  claim 11 , wherein adhering comprises generating a fluorine plasma. 
     
     
       15. The method of  claim 11 , wherein forming the polysilazane material comprises depositing the polysilazane material at room temperature, followed by a baking treatment between about 100° C. to about 350° C. 
     
     
       16. The method of  claim 11 , wherein increasing a porosity of the polysilazane material comprises annealing the silicon dioxide liner and the polysilazane material. 
     
     
       17. The method of  claim 11 , wherein isotropically etching comprises using one or more of (a) vapor phase cleaning using hydrofluoric acid, and (b) wet etching using hydrofluoric acid.