Wiring substrate and semiconductor device

Abstract

A wiring substrate including an insulation layer, a connection terminal projecting from an upper surface of the insulation layer, a protective insulation layer formed on the upper surface of the insulation layer covering a lower side surface of the connection terminal, and a cover layer covering an upper side surface and an upper surface of the connection terminal exposed from the protective insulation layer. The protective insulation layer includes an upper surface defining a protrusion bulged upward around the connection terminal. The protrusion includes a peak, a first slope inclined downward from the peak and extending toward the connection terminal, and a second slope inclined downward from the peak and extending away from the connection terminal. The cover layer further covers the first slope, the peak, and a part of the second slope.

The invention claimed is: 
     
       1. A wiring substrate comprising:
 an insulation layer; 
 a rod-shaped connection terminal projecting upward from an upper surface of the insulation layer, wherein the connection terminal is adapted to be connected to an electronic component; 
 a protective insulation layer formed on the upper surface of the insulation layer to cover a lower side surface of the connection terminal; 
 a cover layer that covers an upper surface of the connection terminal and an upper side surface of the connection terminal which are exposed from the protective insulation layer; 
 wherein
 the protective insulation layer includes an upper surface that defines a protrusion bulged upward around the connection terminal, 
 the protrusion includes
 a peak, 
 a first slope inclined downward from the peak and extending toward the connection terminal that is located in the proximity of the peak, and 
 a second slope inclined downward from the peak and extending away from the connection terminal that is located in the proximity of the peak, and 
 
 the cover layer further covers the first slope, the peak, and a part of the second slope. 
 
 
     
     
       2. The wiring substrate according to  claim 1 , wherein the cover layer includes a lower end that is spread out along the second slope. 
     
     
       3. The wiring substrate according to  claim 1 , wherein the lower side surface of the connection terminal covered by the protective insulation layer has a larger surface roughness than the upper side surface and the upper surface of the connection terminal that are exposed from the protective insulation layer. 
     
     
       4. The wiring substrate according to  claim 1 , wherein
 the cover layer includes a stack of metal layers, 
 one of the metal layers is a nickel layer formed from a metal material including nickel, and 
 the nickel layer covers the first slope, the peak, and the part of the second slope. 
 
     
     
       5. The wiring substrate according to  claim 1 , further comprising:
 a wiring layer covered by the insulation layer; 
 a through hole extending through the insulation layer in a thickness-wise direction to expose an upper surface of the wiring layer; 
 a metal film that continuously covers the upper surface of the wiring layer exposed by the through hole, a wall surface of the insulation layer defining the through hole, and the upper surface of the insulation layer; and 
 a via wiring formed on the metal film within the through hole, wherein the through hole is filled with the via wiring; 
 wherein the connection terminal is formed on an upper surface of the via wiring and on an upper surface of the metal film outside the through hole. 
 
     
     
       6. The wiring substrate according to  claim 1 , wherein the first slope includes elongated projections arranged next to one another and extending from the peak toward the connection terminal, wherein the elongated projections form a corrugation in the first slope. 
     
     
       7. A semiconductor device comprising:
 the wiring substrate according to  claim 1 ; and 
 an electronic component mounted on the wiring substrate, wherein the electronic component includes a circuit formation surface on which a connection terminal is formed; 
 wherein the connection terminal of the electronic component is electrically connected to the cover layer of the wiring substrate by a solder layer.