Semiconductor devices having fin field effect transistor (FinFET) structures and manufacturing and design methods thereof

Abstract

Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a fin extending from a substrate; 
 a first active gate electrode over the fin; 
 a first channel region overlapped by the first active gate electrode; 
 a first inactive gate electrode over the fin, the first inactive gate electrode being adjacent to the first active gate electrode such that no intermediate gate electrodes exist between the first inactive gate electrode and the first active gate electrode; 
 a second channel region overlapped by the first inactive gate electrode; 
 a first recess in the fin between the first active gate electrode and the first inactive gate electrode; and 
 a semiconductor material in the first recess, the semiconductor material having a different lattice constant than the fin, wherein the semiconductor material has a first edge and a second edge opposite to each other, wherein the first edge and the second edge are in contact with a third edge of the first channel region and a fourth edge of the second channel region, respectively. 
 
     
     
       2. The semiconductor device of  claim 1 , further comprising a second active gate electrode over the fin, the first inactive gate electrode being interposed between the first active gate electrode and the second active gate electrode. 
     
     
       3. The semiconductor device of  claim 2 , further comprising a second recess interposed between the second active gate electrode and the first inactive gate electrode. 
     
     
       4. The semiconductor device of  claim 2 , further comprising a second inactive gate electrode over the fin, the second inactive gate electrode being interposed between the first active gate electrode and the second active gate electrode. 
     
     
       5. The semiconductor device of  claim 4 , further comprising a second recess interposed between the first inactive gate electrode and the second inactive gate electrode, the second recess being filled with the semiconductor material. 
     
     
       6. The semiconductor device of  claim 5 , further comprising:
 a dielectric layer over the first active gate electrode, the second active gate electrode, the first inactive gate electrode, and the second inactive gate electrode; and 
 a contact extending through the dielectric layer to the semiconductor material in the second recess. 
 
     
     
       7. The semiconductor device of  claim 1 , wherein the first inactive gate electrode extends over a plurality of fins. 
     
     
       8. A semiconductor device, comprising:
 a first active fin field effect transistor (FinFET), the first active FinFET comprising:
 a first fin, the first fin comprising a first semiconductive material; and 
 a first channel comprising the first semiconductive material, the first channel being over the first fin; 
 
 an electrically inactive FinFET structure disposed over the first fin proximate the first active FinFET, wherein the electrically inactive FinFET structure comprises a second channel; and 
 a second semiconductive material disposed between the first active FinFET and the electrically inactive FinFET structure, the second semiconductive material being different than the first semiconductive material, wherein the second semiconductive material, the first channel, and the second channel are at a same level, and are interconnected to form a continuous semiconductor region. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the second semiconductive material is disposed in a trench of the first fin. 
     
     
       10. The semiconductor device of  claim 8 , further comprising:
 a second active FinFET, the second active FinFET comprising the first fin; and 
 one or more additional electrically inactive FinFET structures interposed between the first active FinFET and the second active FinFET. 
 
     
     
       11. The semiconductor device of  claim 10 , wherein the second semiconductive material is disposed between adjacent ones of the electrically inactive FinFET structure and the one or more additional electrically inactive FinFET structures. 
     
     
       12. The semiconductor device of  claim 8 , wherein the electrically inactive FinFET structure comprises an inactive gate electrode, the inactive gate electrode extending over a plurality of fins. 
     
     
       13. The semiconductor device of  claim 8 , wherein the first active FinFET comprises a portion of an electrostatic discharge (ESD) circuit. 
     
     
       14. The semiconductor device of  claim 13 , wherein the ESD circuit comprises an ESD circuit for a logic device, an analog device, a memory device, or an input/output (I/O) circuit. 
     
     
       15. The semiconductor device of  claim 8 , wherein the first active FinFET is a diode. 
     
     
       16. A semiconductor device, comprising:
 a first set of fins extending from a substrate, the first set of fins being parallel to each other; 
 a first active gate electrode extending over the first set of fins; 
 a first channel region directly underlying the first active gate electrode; 
 a second active gate electrode extending over the first set of fins, the first active gate electrode being parallel to the second active gate electrode; 
 a first inactive gate electrode extending over one or more of the first set of fins, the first inactive gate electrode being interposed between the first active gate electrode and the second active gate electrode; 
 a second channel region directly underlying the first inactive gate electrode; 
 a recess in a first fin of the first set of fins, the recess being interposed between the first inactive gate electrode and the first active gate electrode; and 
 a semiconductor material in the recess, the semiconductor material having a different lattice constant than the substrate, wherein the semiconductor material has a first edge and a second edge opposite to each other, wherein the first edge and the second edge are in contact with a third edge of the first channel region and a fourth edge of the second channel region, respectively. 
 
     
     
       17. The semiconductor device of  claim 16 , further comprising a second inactive gate electrode extending over a second set of fins, the first inactive gate electrode and the second inactive gate electrode having a same longitudinal axis, the first inactive gate electrode being discontinuous from second inactive gate electrode. 
     
     
       18. The semiconductor device of  claim 17 , wherein the first active gate electrode extends over the second set of fins. 
     
     
       19. The semiconductor device of  claim 17 , further comprising a third inactive gate electrode extending over the first set of fins, the third inactive gate electrode being interposed between the first inactive gate electrode and the second active gate electrode. 
     
     
       20. The semiconductor device of  claim 19 , further comprising another recess in the first fin, the another recess being interposed between the first inactive gate electrode and the third inactive gate electrode.