Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

We claim: 
     
       1. A semiconductor device, comprising:
 a fin extending on a substrate along a first direction; 
 shallow trench isolation regions on the substrate on both sides of a lower portion of the fin extending along the first direction, wherein the top of the fin extends above the top of the shallow trench isolation regions forming an upper portion of the fin; 
 a gate extending along a second direction across the fin; and 
 source/drain regions and a gate spacer on the fin at opposite sides of the gate, 
 wherein the upper portion of the fin has a smaller thickness along the second direction than the lower portion of the fin; and 
 wherein the fin has a recess on the top where the fin intersects the gate and there is a surface layer in the recess of the fin and on both sidewalls of the upper portion of the fin. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the surface layer comprises a high mobility material, which comprises Ge, GaAs, InP, GaSb, InAs, InSb, Site, Si:C, SiGe:C, Strained-Si, GeSn, GeSiSn, or a combination thereof. 
     
     
       3. The semiconductor device according to  claim 1 , wherein the surface layer is in a multi-layer structure. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the surface layer has a thickness that fills the recess of the fin to form a substantially planar surface. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the depth of the recess is less than ¼ of the thickness of the fin and greater than 1/10 of the thickness of the fin. 
     
     
       6. A semiconductor device, comprising:
 a plurality of fins extending on a substrate along a first direction; 
 a gate extending along a second direction across each of the fins; and 
 source/drain regions and a gate spacer on the fins at opposite sides of the gate, 
 wherein the fins have a recess on the top and/or sidewalls where the fins intersect the gate, and there is a surface layer in the recess of the fins. 
 
     
     
       7. The semiconductor device according to  claim 6 , wherein the surface layer comprises a high mobility material, which comprises Ge, GaAs, InP, GaSb, InAs, InSb, Site, Si:C, SiGe:C, Strained-Si, GeSn, GeSiSn, or a combination thereof. 
     
     
       8. The semiconductor device according to  claim 6 , wherein the surface layer is in a multi-layer structure. 
     
     
       9. The semiconductor device according to  claim 6 , wherein the depth of the recess is less than ¼ of the thickness of the fins and greater than 1/10 of the thickness of the fins. 
     
     
       10. The semiconductor device according to  claim 6 , wherein the surface layer has a thickness that fills the recess of the fins to form a substantially planar surface. 
     
     
       11. A semiconductor device, comprising:
 a plurality of fins extending on a substrate along a first direction; 
 a gate extending along a second direction across each of the fins; and 
 source/drain regions and a gate spacer on the fins at opposite sides of the gate, 
 wherein the fins have a recess on the top where the fins intersect the gate, and there is a surface layer in the recess on the top of the fins, and the top of the fins is higher than Shallow Trench Isolation (STI) on the substrate. 
 
     
     
       12. The semiconductor device according to  claim 11 , wherein the surface layer comprises a high mobility material, which comprises Ge, GaAs, InP, GaSb, InAs, InSb, SiGe, Si:C, SiGe:C, Strained-Si, GeSn, GeSiSn, or a combination thereof. 
     
     
       13. The semiconductor device according to  claim 11 , wherein the surface layer is in a multi-layer structure. 
     
     
       14. The semiconductor device according to  claim 11 , wherein the surface layer has a thickness that fills the recess of the fins to form a substantially planar surface. 
     
     
       15. The semiconductor device according to  claim 11 , wherein the depth of the recess is less than ¼ of the thickness of the fins and greater than 1/10 of the thickness of the fins.