Inverted-T shaped via for reducing adverse stress-migration effects

Abstract

A semiconductor interconnect structure is formed as a via with an inverted-T shape to increase the reliability of the interface between the interconnect structure and an underlying electrically conductive, e.g., copper (Cu), layer of material. The inverted-T shape effectively increases a bottom critical dimension of the via, thereby reducing and/or eliminating via degradation of the interconnect structure caused by voids in the electrically conductive layer introduced during high-temperature or stress-migration baking.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 an electrically conductive layer disposed in the structure; 
 a capping layer that overlays the electrically conductive layer, the capping layer having an opening extending through the entire capping layer, the opening being in the shape of a truncated cone having a first taper angle; 
 a layer of dielectric material formed over the capping layer, the layer of dielectric material having an opening in the shape of a truncated inverted cone having a second taper angle, wherein the second taper angle is different from the first taper angle; and
 an interconnect structure disposed in the layer of dielectric material and the capping layer, the interconnect structure making contact with the electrically conductive layer, 
 
 wherein the interconnect structure has a first dimension at a bottom surface of the dielectric layer and a second dimension at a top surface of the capping layer that is wider than the first dimension. 
 
     
     
       2. The semiconductor structure as set forth in  claim 1 , wherein the interconnect structure has a third dimension at a lower region of the capping layer different than the second dimension. 
     
     
       3. The semiconductor structure as set forth in  claim 2 , wherein the third dimension is wider than the second dimension. 
     
     
       4. The semiconductor structure as set forth in  claim 2 , wherein the third dimension is at a bottom surface of the capping layer. 
     
     
       5. The semiconductor structure as set forth in  claim 2 , wherein the third dimension is not less than the second dimension. 
     
     
       6. The semiconductor structure as set forth in  claim 1 , wherein the interconnect structure comprises a via exhibiting an inverted T-shape. 
     
     
       7. The semiconductor structure as set forth in  claim 1 , wherein the electrically conductive layer comprises a material selected from the group consisting of copper, aluminum, doped silicon and mixtures thereof. 
     
     
       8. The semiconductor structure as set forth in  claim 1 , wherein the capping layer comprises one or more compounds of silicon chemical composition. 
     
     
       9. The semiconductor structure as set forth in  claim 1 , wherein the capping layer comprises nitride. 
     
     
       10. The semiconductor structure as set forth in  claim 1 , wherein the layer of dielectric material comprises one or more of an oxide of silicon, tetraethyl orthosilicate, and a low-k oxide. 
     
     
       11. The semiconductor structure as set forth in  claim 2 , wherein the interconnect structure further exhibits a fourth dimension at a top surface of the dielectric layer, the fourth dimension being not less than the first dimension, whereby bridging of tops of adjacent vias is avoided. 
     
     
       12. A semiconductor structure including an interconnect structure having an inverted shape in the semiconductor structure comprising:
 an electrically conductive layer; 
 a capping layer disposed over the electrically conductive layer, the capping layer having a first opening extending through the entire capping layer, the first opening being in the shape of a truncated cone defined by a first taper angle; 
 a dielectric layer overlaying the capping layer, the dielectric layer having a second opening in the shape of a truncated inverted cone defined by a second taper angle, wherein the second taper angle is smaller than the first taper angle; and 
 an interconnect structure formed within the first and second openings and having a first dimension at the bottom surface of the dielectric layer, a second dimension at a top surface of the capping layer and a third dimension at the bottom of the capping layer, wherein the second dimension is greater than the first dimension. 
 
     
     
       13. The semiconductor structure as set forth in  claim 1 , wherein the capping layer and the dielectric layer are in direct contact. 
     
     
       14. The semiconductor structure as set forth in  claim 12 , wherein the capping layer and the dielectric layer are in direct contact.