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US9978839B2ActiveUtilityPatentIndex 52

Method of manufacturing a MOSFET on an SOI substrate

Assignee: RENESAS ELECTRONICS CORPPriority: Jan 23, 2012Filed: Jun 21, 2017Granted: May 22, 2018
Est. expiryJan 23, 2032(~5.6 yrs left)· nominal 20-yr term from priority
Inventors:YAMAMOTO YOSHIKIMAKIYAMA HIDEKIIWAMATSU TOSHIAKITSUNOMURA TAKAAKI
H10P 30/20H10W 20/069H10W 15/01H10W 15/00H01L 29/665H01L 21/265H01L 29/1083H01L 29/66537H01L 29/66477H01L 21/74H01L 21/823807H01L 29/6659H01L 21/84H01L 29/0649H01L 21/823814H01L 29/7833H10D 86/201H10D 86/01H10D 84/0167H10D 84/0128H10D 84/038H10D 84/017H10D 84/013H10D 64/519H10D 64/259H10D 64/021H10D 64/018H10D 64/017H10D 64/015H10D 62/157H10D 62/151H10D 62/115H10D 30/6744H10D 30/6743H10D 30/6715H10D 30/6704H10D 30/657H10D 30/601H10D 30/0323H10D 30/0321H10D 30/0314H10D 30/0275H10D 30/0243H10D 30/0227H10D 30/0217H10D 30/0212H10D 30/031H10D 30/021H10D 62/371
52
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Cited by
38
References
7
Claims

Abstract

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of manufacturing a semiconductor device including a semiconductor substrate, a first insulating film formed over the semiconductor substrate and a semiconductor layer formed over the first insulating film, comprising steps of:
 (a) forming a gate insulating film of a field effect transistor over the semiconductor layer; 
 (b) forming a gate electrode of the field effect transistor over the gate insulating film; 
 (c) forming a second insulating film over the semiconductor layer and a side surface of the gate electrode; 
 (d) providing a first side wall including the second insulating film and a third insulating film by forming the third insulating film over the semiconductor layer and the side surface of the gate electrode through the second insulating film, the third insulating film made of a different material from the second insulating film; 
 (e) after the step (d), forming an epitaxial layer over the semiconductor layer and a side of the first side wall; 
 (f) after the step (e), removing the third insulating film such that the second insulating film located between the semiconductor layer and the third insulating film is remained; 
 (g) after the step (f), forming a first impurity region of a first conductivity type in the first semiconductor layer through the second insulating film by an ion implantation method; 
 (h) after the step (g), providing a second side wall including the second insulating film and a fourth insulating film by forming the fourth insulating film over the semiconductor layer and the side surface of the gate electrode through the second insulating film, the fourth insulating film made of a different material from the second insulating film; and 
 (i) after the step (h), forming a second impurity region of the first conductivity type in the epitaxial layer and the first semiconductor layer by an ion implantation method, 
 wherein the first impurity region is a part of a source region of the field effect transistor or a part of a drain region of the field effect transistor, and 
 wherein the second impurity region is a part of the source region of the field effect transistor or a part of the drain region of the field effect transistor, and has larger impurity concentration than the first impurity region. 
 
     
     
       2. A method of manufacturing a semiconductor device according to  claim 1 , further comprising a step of:
 (j) after the step (i), forming silicide layers over the gate electrode and the epitaxial layer. 
 
     
     
       3. A method of manufacturing a semiconductor device according to  claim 1 , further comprising a step of:
 (k) between the steps (f) and (h), forming a third impurity region of a second conductivity type being opposite to the first conductivity type in the semiconductor substrate by an ion implantation method. 
 
     
     
       4. A method of manufacturing a semiconductor device according to  claim 3 ,
 wherein the first conductivity type is an n-type, and 
 wherein the second conductivity type is a p-type. 
 
     
     
       5. A method of manufacturing a semiconductor device according to  claim 1 ,
 wherein the second insulating film includes a silicon oxide film, and 
 wherein the third insulating film includes a silicon nitride film. 
 
     
     
       6. A method of manufacturing a semiconductor device according to  claim 1 ,
 wherein the second insulating film includes a silicon oxide film, and 
 wherein the fourth insulating film includes a silicon nitride film. 
 
     
     
       7. A method of manufacturing a semiconductor device according to  claim 1 ,
 wherein the first conductivity type is an n-type.

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