Memory cell array semiconductor integrated circuit device

Abstract

Memory cells having a stable write operation are formed in an array on a CMOS gate array semiconductor substrate. Each memory cell includes mutually adjacent transistors from a first pair of complementary conductivity type MOS transistor rows. These transistors are used to form a flip-flop and first and second access gates. The memory cell further includes mutually adjacent MOS transistors from a second pair of complementary conductivity type MOS transistor rows. These transistors are used to form an inverter and a third access gate connected to the output of the inverter. The input of the inverter is connected to one end of the flip-flop. The inputs of the first and second access gates are connected to bit lines through which complementary data signals are applied. The gates of the first and second access gate transistors are connected to a write word line. The third access gate is connected to a readout signal providing bit line, and the gate of the third access gate MOS transistor is connected to a read word line.

What is claimed is: 
     
       1. A memory cell array comprising: at least a first memory cell including at least first and second pairs of rows of transistors;   each of said pairs including first and second rows having first and second conductivity types, respectively;   first, second, third and fourth transistors in said first row of said first pair;   fifth and sixth transistors in said second row of said first pair,   each of said first, second, third and fourth transistors being adjacent and sharing source/drain regions with an adjacent one of said first, second, third and fourth transistors;   each of said fifth and sixth transistors being adjacent and sharing a source/drain region;   said second and fifth transistors being connected in series between first and second reference voltages to form a first inverter;   said third and sixth transistors being connected in series between said first and second reference voltages to form a second inverter;   an input of said first inverter being connected to an output of said second inverter;   an input of said second inverter being connected to an output of said first inverter;   said first and fourth transistors having sources connected to first and second bit lines, respectively;   said first and fourth transistors having gates connected to a write word line;   said first and fourth transistors having drains connected to said input of said first inverter and said input of said second inverter, respectively;   seventh and eighth transistors in said first and second row of said second pair, respectively;   said seventh and eighth transistors being connected in series between said first and second reference voltages to form a third inverter;   an input of said third inverter being connected to said output of said second inverter; and   a ninth transistor having a drain connected to an output of said third inverter, a source connected to a read out line, and a gate connected to a read word line.   
     
     
       2. A memory cell array according to claim 1, further comprising: a second memory cell including a first transistor through a ninth transistor; and   said first transistor of said first memory cell shares its source region with said first transistor of said second memory cell.   
     
     
       3. A memory cell array according to claim 2, wherein said fourth transistor of said first memory cell shares its source region with said fourth transistor of said second memory cell. 
     
     
       4. A memory cell array according to claim 2, wherein said ninth transistor of said first memory cell shares its drain region with said ninth transistor of said second memory cell. 
     
     
       5. A memory cell array according to claim 2, further comprising: said seventh transistor of said first memory cell shares its drain region with said seventh transistor of said second memory cell; and   said eighth transistor of said first memory cell shares its drain region with said eighth transistor of said second memory cell.   
     
     
       6. A memory cell array according to claim 1, wherein said third inverter includes a combination of a plurality of parallel transistors from said first row of said second pair and a plurality of parallel transistors from said second row of said second pair. 
     
     
       7. A memory cell array according to claim 2, wherein said first memory cell is symmetrical to said second memory cell. 
     
     
       8. A memory cell array according to claim 1, wherein said eighth and ninth transistors share a drain region.