Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Abstract

A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor on a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the tint, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

We claim: 
     
       1. An integrated high-voltage bipolar power transistor and vertical low-voltage MOS power transistor structure, comprising: an N+ type semiconductor substrate;   an overlying semiconductor layer on said N+ type semiconductor substrate and comprising a first N type epitaxial layer and a second N type epitaxial layer grown on said first N type epitaxial layer;   a first dopant-diffusion P type region formed in said first N type epitaxial layer in a vicinity of a boundary between said first N type epitaxial layer and said second N type epitaxial layer;   a second P type region connecting said first P type region with a surface of the structure and located in said second N type epitaxial layer, said first and second regions constituting a base region of a bipolar transistor of said structure;   a third completely buried N+ type region adjoining at a lower side said first P type region, substantially more doped than said second epitaxial layer, located astride said boundary between said first and second epitaxial layers, and constituting an emitter region of the bipolar transistor, a portion of said second epitaxial layer being disposed between said third region and said surface with said second region extending alongside said portion of said second epitaxial layer to said surface;   body and source regions of an MOS transistor of said structure located in said portion of said second epitaxial layer in a vicinity of said surface and above said third region spaced from said second P type region;   means connected to said portion of said epitaxial layer between said body and source regions to form from said portion a drain region of said MOS transistor; and   means connected to said N+ type semiconductor substrate to form from said substrate a collector of said bipolar transistor.   
     
     
       2. An integrated high-voltage bipolar power transistor and horizontal low-voltage MOS power transistor structure in an emitter switching configuration, comprising: an N+ type semiconductor substrate;   an N- type epitaxial layer grown on said N+ type semiconductor substrate;   a first dopant-diffusion P+ type region formed in said N- type epitaxial layer at a surface thereof and constituting a base of a bipolar transistor of said structure;   a second N+ type region formed within said first P+ type region and adjoining said first P+ type region at a bottom and sides of said second N+ type region and terminating at said surface to constitute an emitter of said bipolar transistor;   a third P+ type region formed in said N- type epitaxial layer at said surface, spaced from said first P+ type region;   a fourth N+ type region formed within said third P+ type region and adjoining said third P+ type region at a bottom and sides of said fourth N+ type region and terminating at said surface, said fourth N+ type region forming a source of an MOS transistor of said structure;   a fifth N+ type region formed within said third P+ type region and adjoining said third P+ type region at a bottom and sides of said fifth N+ type region and terminating at said surface, said fifth N+ type region being spaced from said fourth N+ type region and forming a drain of said MOS transistor of said structure;   a conductor track on said surface connecting said emitter and said drain; and   means connected to said N+ type semiconductor substrate to form from said substrate a collector of said bipolar transistor. .Iadd.   
     
     
       3.  An integrated circuit device structure, comprising, in a substantially monocrystalline body of semiconductor between first and second surfaces thereof: a collector, extending to said first surface, which is heavily doped with a first conductivity type;   a drift region, overlying said collector, which has said first conductivity type and is more lightly doped than said collector;   a base region, overlying said drift region, which has a second conductivity type;   an emitter region, overlying said base region, which is heavily doped with said first conductivity type;   a drain region, overlying said emitter region, which has said first conductivity type and is more lightly doped than said emitter region;   a body region, overlying said drain region, which has said second conductivity type;   a source region, overlying said body region, which is heavily doped with said first conductivity type;   a gate electrode which is in proximity to said second surface of said monocrystalline body, and which is capacitively coupled to said body region to induce therein a channel region which provides a current path from said source region and said drain region..Iaddend..Iadd.   
     
     
       4.  The device structure of claim 3, wherein said first conductivity type is N-type and said second conductivity type is P-type..Iaddend..Iadd.5. The device structure of claim 3, wherein said gate electrode is insulated 
     
     
        from said body region..Iaddend..Iadd.6.  An integrated circuit device structure, comprising, in a substantially monocrystalline body of semiconductor between first and second surfaces thereof; a VDMOS device, comprising a respective first diffusion of a first conductivity type in proximity to said first surface of said monocrystalline body, and a second diffusion of a first conductivity type within said body, and a gate electrode capacitively coupled to regulate current flow between said first and second diffusions;   a high-voltage bipolar device, comprising a respective first diffusion of a first conductivity type in proximity to said second surface of said monocrystalline body, and a second diffusion of a first conductivity type within said body, and a base electrode interposed to regulate current flow between said first and second diffusions;   wherein said VDMOS device directly overlies said bipolar device, and   wherein said second diffusion of said VDMOS device is merged with said second diffusion of said bipolar device..Iaddend..Iadd.7. The device structure of claim 6, wherein said first conductivity type is N-type and a   
     
     
        second conductivity type is P-type..Iaddend..Iadd.8.  The device structure of claim 6, wherein said gate electrode is insulated from said body 
     
     
        region..Iaddend..Iadd.9.  A merged power transistor structure comprising: a first active device located near a first surface of a monolithic semiconductor body, and providing conduction between said first surface and a first buried layer of a first conductivity type, whose potential is controlled by said conduction of said first active device; and   a second active device located within said monolithic body beneath said first device, and providing bipolar conduction between said first buried layer and a second surface of the monolithic body; said second active device including a second buried layer, beneath said first buried layer, which forms a base-emitter junction with said first layer; conduction of said first device controlling the bias of said base-emitter junction, and thereby controlling conduction of said second active device;   whereby said first active device provides control of current, and said second active device provides high-voltage standoff with low on-resistance..Iaddend.