Method of manufacturing inversion type IC's and IC module using same

Abstract

A method of manufacturing inversion ICs includes the steps of connecting a first electrode pad group of a semiconductor chip to a second lead group via wires, connecting a second electrode pad group of the semiconductor chip to a first lead group via wires, sealing the semiconductor chip, the first and second lead groups, and the wires in a resin so that the outer lead portions of the leads are exposed, and bending the outer lead portions of the leads toward the bottom surface of the semiconductor chip. An IC module includes a mounting substrate, a standard IC mounted on the top surface of the mounting substrate, an inversion IC mounted on the bottom surface of the mounting substrate so that the leads providing connections to the same functions in the standard and inversion ICs are at the same point on opposite sides of the mounting substrate, and a plurality of connecting members on the mounting substrate, electrically connecting the opposed leads of the standard IC and the leads of the inversion IC together.

What is claimed is: 
     
       1. The method of making pairs of packaged semiconductor chips having inverted lead relationships for direct mounting and parallel electrical connection of the pairs of packaged semiconductor chips with the packaged semiconductor chips opposed to each other, the method comprising: preparing identical first and second semiconductor chips, each semiconductor chip including opposed top and bottom surfaces.Iadd., opposed first and second edges, .Iaddend.and first and second rows of electrode pads disposed on the top surface .Iadd.proximate the first and second edges, respectively.Iaddend.;   mounting the first semiconductor chip on a die pad of a first lead frame, the first lead frame including first and second rows of peripherally disposed leads, the first row of leads being disposed proximate .Iadd.the first edge and .Iaddend.the first row of electrode pads of the first semiconductor chip and the second row of leads being disposed proximate .Iadd.the second edge and .Iaddend.the second row of electrode pads of the first semiconductor chip;   connecting the electrode pads of the first semiconductor chip in the first row to corresponding leads in the first row of leads of the first lead frame with wires and connecting the electrode pads of the first semiconductor chip in the second row to corresponding leads in the second row of leads of the first lead frame with wires;   encapsulating the first semiconductor chip, the die pad of the first lead frame, the wires, and parts of the leads of the first lead frame in a resin with part of the leads of the first lead frame extending from the resin; and   bending the leads protruding from the resin encapsulating the first semiconductor chip toward the bottom surface of the first semiconductor chip;   mounting the second semiconductor chip on a die pad of a second lead frame, the second lead frame including first and second rows of peripherally disposed leads, .Iadd.the first row of leads being disposed proximate the first edge and the second leads being disposed proximate the second edge, .Iaddend.the leads of the second lead frame extending across at least part of the die pad of the second lead frame and spaced from the top surface of the second semiconductor chip, the first row of leads including ends proximate the second row of electrode pads of the second semiconductor chip, and the second row of leads including ends proximate the first row of electrode pads of the second semiconductor chip;   connecting the electrode pads of the second semiconductor chip in the first row to corresponding leads in the second row of leads of the second lead frame with wires and connecting the electrode pads of the second semiconductor chip in the second row to corresponding leads in the first row of leads of the second lead frame with wires;   encapsulating the second semiconductor chip, the die pad of the second lead frame, the wires, and parts of the leads of the second lead frame in a resin with part of the leads of the second lead frame extending from the resin; and   bending the leads protruding from the resin encapsulating the second semiconductor chip toward the bottom surface of the second semiconductor chip .Iadd.whereby the encapsulated first and second semiconductor chips have inverted lead relationships.Iaddend..   
     
     
       2. A method of making . .pair.!. .Iadd.pairs .Iaddend.of packaged semiconductor chips having inverted lead relationships for direct mounting and parallel electrical connection of the pairs of packaged semiconductor chips with the packaged semiconductor chips opposed to each other, the method comprising: preparing identical first and second semiconductor chips, each semiconductor chip including opposed top and bottom surfaces.Iadd., opposed first and second edges, .Iaddend.and a first row of electrode pads, alternating electrode pads in the first row being designated odd and even pads, disposed on the top surface;   mounting the first semiconductor chip on a die pad of a first lead frame, the first lead frame including first and second rows of peripherally disposed leads, the first row of leads being disposed proximate the .Iadd.first edge and the .Iaddend.odd electrode pads of the first semiconductor chip.Iadd., .Iaddend.and the second row of leads being disposed proximate .Iadd.the second edge .Iaddend.the even electrode pads of the semiconductor chip;   connecting the odd electrode pads of the first semiconductor chip to corresponding leads in the first row of leads of the first lead frame with wires and connecting the even electrode pads of the first semiconductor chip to corresponding leads in the second row of leads of the first lead frame with wires;   encapsulating the first semiconductor chip, the die pad of the first lead frame, the wires, and parts of the leads of the first lead frame in a resin with part of the leads of the first lead frame extending from the resin; and   bending the leads protruding from the resin encapsulating the first semiconductor chip toward the bottom surface of the first semiconductor chip;   mounting the second semiconductor chip on a die pad of a second lead frame, the second lead frame including first and second rows of peripherally disposed leads, the first row of leads of the second lead frame being disposed proximate .Iadd.the first edge and .Iaddend.proximate the even electrode pads and the second row of leads of the second lead frame being disposed proximate the odd electrode pads;   connecting the even electrode pads of the second semiconductor chip to corresponding leads in the first row of leads of the second lead frame with wires and connecting the odd electrode pads of the second semiconductor chip to corresponding leads in the second row of leads of the second lead frame with wires;   encapsulating the second semiconductor chip, the die pad of the second lead frame, the wires, and parts of the leads of the second lead frame in a resin with part of the leads of the second lead frame extending from the resin; and   bending the leads protruding from the resin encapsulating the second semiconductor chip toward the bottom surface of the second semiconductor chip .Iadd.whereby the encapsulated first and second semiconductor chips have inverted lead relationships.Iaddend..   
     
     
       3. A packaged semiconductor chip module comprising: a mounting substrate having opposed first and second surfaces;   a non-inverted packaged semiconductor chip mounted on the first surface of the mounting substrate, the non-inverted . .package.!. .Iadd.packaged .Iaddend.semiconductor chip including a plurality of leads arranged in first and second rows, a first semiconductor chip having opposed .Iadd.first and second edges and opposed .Iaddend.top and bottom surfaces, a plurality of electrode pads arranged in first and second rows on the top surface of the first semiconductor chip .Iadd.proximate the first and second edges, respectively.Iaddend., and wires connecting leads of the first and second rows of leads to corresponding electrode pads of the first and second rows of electrode pads, respectively, each of the leads including an outer lead portion extending from the . .noninverted.!. .Iadd.non-inverted .Iaddend.packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the first semiconductor chip and the bottom surface of the first semiconductor chip faces the first surface of the mounting substrate;   an inverted packaged semiconductor chip mounted on the second surface of the mounting substrate and including a plurality of leads arranged in first and second rows, a second semiconductor chip identical to the first semiconductor chip and having .Iadd.opposed first and second edges and .Iaddend.opposed top and bottom surfaces, a plurality of electrode pads arranged in first and second rows on the top surface of the semiconductor chip .Iadd.proximate the first and second edges, respectively.Iaddend., and wires connecting leads of the second and first rows of leads to corresponding electrode pads of the first and second rows of electrode pads, respectively, each of the leads including an outer lead portion extending from the inverted packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the second semiconductor chip and the bottom surface of the second semiconductor chip faces the second surface of the mounting substrate; and   a plurality of connecting members on and penetrating the mounting substrate, electrically connecting leads of the . .noninverted.!. .Iadd.non-inverted .Iaddend.packaged semiconductor chip to corresponding leads of the inverted packaged semiconductor chip.   
     
     
       4. The packaged semiconductor chip module of claim 3 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and parts of the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and is spaced from the top surface of the second semiconductor chip. 
     
     
       5. The packaged semiconductor chip module of claim 4 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted semiconductor chip packages. 
     
     
       6. The packaged semiconductor chip module of claim 4 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from four sides of each of the inverted and non-inverted semiconductor chip packages. 
     
     
       7. A packaged semiconductor chip module comprising: a mounting substrate having opposed first and second surfaces;   a non-inverted packaged semiconductor chip mounted on the first surface of the mounting substrate, the non-inverted packaged semiconductor chip including a plurality of leads arranged in first and second rows, a first semiconductor chip having opposed .Iadd.first and second edges and opposed .Iaddend.top and bottom surfaces, a plurality of electrode pads arranged in first and second rows on the top surface of the first semiconductor chip .Iadd.proximate the first and second edges, respectively.Iaddend., and wires connecting leads of the first and second rows of leads to corresponding electrode pads of the first and second rows of electrode pads, respectively, each of the leads including an outer lead portion extending from the . .noninverted.!. .Iadd.non-inverted .Iaddend.packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the first semiconductor chip and the bottom surface of the first semiconductor chip faces the first surface of the mounting substrate;   an inverted packaged semiconductor chip mounted on the first surface of the mounting substrate and including a plurality of leads arranged in first and second rows, a second semiconductor chip identical to the first semiconductor chip and having .Iadd.opposed first and second edges and .Iaddend.opposed top and bottom surfaces, a plurality of electrode pads arranged in first and second rows on the top surface of the semiconductor chip .Iadd.proximate the first and second edges, respectively.Iaddend., and wires connecting leads of the second and first rows of leads to corresponding electrode pads of the first and second rows of electrode pads, respectively, each of the leads including an outer lead portion extending from the inverted packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the second semiconductor chip and the bottom surface of the second semiconductor chip faces the first surface of the mounting substrate; and   a plurality of connecting members on and penetrating the mounting substrate, electrically connecting leads of the . .noninverted.!. .Iadd.non-inverted .Iaddend.packaged semiconductor chip to corresponding leads of the inverted packaged semiconductor chip.   
     
     
       8. The packaged semiconductor chip module of claim 7 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and is spaced from the top surface of the second semiconductor chip. 
     
     
       9. The packaged semiconductor chip module of claim 8 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted semiconductor chip packages. 
     
     
       10. The packaged semiconductor chip module of claim 8 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from four sides of each of the inverted and non-inverted semiconductor chip packages. 
     
     
       11. A packaged semiconductor chip module comprising: a mounting substrate having opposed first and second surfaces;   a non-inverted packaged semiconductor chip mounted on the first surface of the mounting substrate, the non-inverted packaged semiconductor chip including a plurality of leads arranged in first and second rows, a first semiconductor chip having .Iadd.opposed first and second edges and .Iaddend.opposed top and bottom surfaces, a plurality of electrode pads arranged in a row on the top surface of the first semiconductor chip with alternating electrode pads in the row designated . .as.!. odd and even electrode pads, and wires connecting leads of the first and second rows to corresponding odd and even electrode pads, respectively, each of the leads including an outer lead portion extending from the non-inverted packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the first semiconductor chip and the bottom surface of the first semiconductor chip faces the first surface of the mounting substrate;   an inverted packaged semiconductor chip mounted on the second surface of the mounting substrate and including a plurality of leads arranged in first and second rows, a second semiconductor chip identical to the first semiconductor chip and having .Iadd.opposed first and second edges and .Iaddend.opposed top and bottom surfaces, a plurality of electrode pads arranged in a row on the top surface of the second semiconductor chip with alternating electrode pads in a row designated odd and even electrode pads, and wires connecting leads of the second and first rows to corresponding odd and even electrode pads, respectively, each of the leads including an outer lead portion extending from the inverted packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the second semiconductor chip and the bottom surface of the second semiconductor chip faces the second surface of the mounting substrate; and   a plurality of connecting members on and penetrating the mounting substrate, electrically connecting leads of the . .noninverted.!. .Iadd.non-inverted .Iaddend.packaged semiconductor chip to corresponding leads of the inverted packaged semiconductor chip.   
     
     
       12. The packaged semiconductor chip module of claim 11 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and parts of the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and is spaced from the top surface of the second semiconductor chip. 
     
     
       13. The packaged semiconductor chip module of claim 12 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted semiconductor chip packages. . .14. The packaged semiconductor chip module of claim 12 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from four sides of each of the inverted 
     
     
        and non-inverted semiconductor chip packages..!.15. A packaged semiconductor chip module comprising: a mounting substrate having opposed first and second surfaces;   a non-inverted packaged semiconductor chip mounted on the first surface of the mounting substrate, the non-inverted packaged semiconductor chip including a plurality of leads arranged in first and second rows, a first semiconductor chip having .Iadd.opposed first and second edges and .Iaddend.opposed top and bottom surfaces, a plurality of electrode pads arranged in a row . .with alternating electrode pads designated as odd and even electrode pads.!. on the top surface of the first semiconductor chip with alternating electrode pads in the row designated . .as.!. odd and even electrode pads, and wires connecting leads of the first and second rows to corresponding odd and even electrode pads, respectively, each of the leads including an outer lead portion extending from the non-inverted packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the first semiconductor chip and the bottom surface of the first semiconductor chip faces the first surface of the mounting substrate;   an inverted packaged semiconductor chip mounted on the first surface of the mounting substrate and including a plurality of leads arranged in first and second rows, a second semiconductor chip identical to the first semiconductor chip and having .Iadd.opposed first and second edges and .Iaddend.opposed top and bottom surfaces, a plurality of electrode pads arranged in a row on the top surface of the second semiconductor chip with alternating electrode pads in a row designated odd and even electrode pads, and wires connecting leads of the second and first rows to corresponding odd and even electrode pads, respectively, each of the leads including an outer lead portion extending from the inverted packaged semiconductor chip wherein the outer lead portions of the leads are bent toward the bottom surface of the second semiconductor chip and the bottom surface of the second semiconductor chip faces the first surface of the mounting substrate; and   a plurality of connecting members on and penetrating the mounting substrate, electrically connecting leads of the . .noninverted.!. .Iadd.non-inverted .Iaddend.packaged semiconductor chip to corresponding   
     
     
        leads of the inverted packaged semiconductor chip. 16. The packaged semiconductor chip module of claim 15 wherein each of the non-inverted packaged semiconductor chip and the inverted packaged semiconductor chip includes a resin package encapsulating the first and second semiconductor chips, the wires, and the first and second rows of leads so that outer portions of the leads protrude from the respective packages and each of the leads in the inverted packaged semiconductor chip crosses part of and 
     
     
        is spaced from the top surface of the second semiconductor chip. 17. The packaged semiconductor chip module of claim 16 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted semiconductor chip packages. . .18. The packaged semiconductor chip module of claim 16 wherein the inverted and non-inverted packaged semiconductor chips are substantially rectangular and the outer lead portions extend from four sides of each of the inverted 
     
     
        and non-inverted semiconductor chip packages..!.19. A pair of non-inverted and inverted packaged semiconductor devices wherein, the non-inverted packaged semiconductor device comprises: a plurality of leads arranged in first and second rows;   a first semiconductor chip having opposed first and second edges and opposed top and bottom surfaces and a plurality of electrode pads arranged in first and second rows proximate the first and second edges, respectively, on the top surface of the first semiconductor chip;   wires connecting leads of the first and second rows of leads to corresponding electrode pads of the first and second rows of electrode pads, respectively; and   a resin body encapsulating the first semiconductor chip, the wires, and parts of the leads, each of the leads including an outer lead portion extending outside the resin package wherein the outer lead portions are bent toward the bottom surface of the first semiconductor chip; and     the inverted packaged semiconductor device comprises: a plurality of leads arranged in first and second rows;   a second semiconductor chip identical to the first semiconductor chip and having opposed first and second edges and opposed top and bottom surfaces and a plurality of electrode pads arranged in first and second rows on the top surface of the second semiconductor chip;   wires connecting leads of the second and first rows of leads to corresponding electrode pads of the first and second rows of electrode pads, respectively; and   a resin body encapsulating the second semiconductor chip, the wires, and parts of the leads, each of the leads including an outer lead portion extending outside the resin package wherein the outer lead portions are bent toward the bottom surface of the second semiconductor chip.     
     
     
        .Iadd.     The pair of non-inverted and inverted packaged semiconductor devices of claim 19 wherein each of the leads in the inverted packaged semiconductor device crosses part of and is spaced from the top surface of the second semiconductor chip. .Iaddend..Iadd.21. The pair of non-inverted and inverted packaged semiconductor devices of claim 20 wherein the resin bodies of the inverted and non-inverted packaged semiconductor devices are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted packaged semiconductor devices. .Iaddend..Iadd.22. The pair of non-inverted and inverted packaged semiconductor devices of claim 20 wherein the resin bodies of the inverted and non-inverted packaged semiconductor devices are substantially rectangular and the outer lead portions extend from four sides of each of the inverted and non-inverted packaged semiconductor devices. 
     
     
        .Iaddend..Iadd.23.  A pair of non-inverted and inverted packaged semiconductor devices wherein, the non-inverted packaged semiconductor device comprises: a first semiconductor chip having opposed first and second edges and opposed top and bottom surfaces and a plurality of electrode pads arranged in a row on the top surface of the first semiconductor chip with alternating electrode pads in the row designated odd and even electrode pads;   a plurality of leads arranged in first and second rows proximate the first second edges, respectively;   wires connecting leads of the first and second rows to corresponding odd and even electrode pads, respectively; and   a resin body encapsulating the first semiconductor chip, the wires, and parts of the leads, each of the leads including an outer lead portion extending outside the resin package wherein the outer lead portions are bent toward the bottom surface of the first semiconductor chip; and     the inverted packaged semiconductor device comprises: a second semiconductor chip identical to the first semiconductor chip and having opposed first and second edges and opposed top and bottom surfaces and a plurality of electrode pads arranged in a row on the top surface of the second semiconductor chip with alternating electrode pads in the row designated odd and even electrode pads;   a plurality of leads arranged in first and second rows proximate the first and second edges, respectively;   wires connecting leads of the second and first rows to corresponding odd and even electrode pads, respectively; and   a resin body encapsulating the second semiconductor chip, the wires, and parts of the leads, each of the leads including an outer lead portion extending outside the resin package wherein the outer lead portions are bent toward the bottom surface of the second semiconductor chip.     
     
     
        .Iaddend..Iadd.24.  The pair of non-inverted and inverted packaged semiconductor devices of claim 23 wherein each of the leads in the inverted packaged semiconductor device crosses part of and is spaced from the top surface of the second semiconductor chip. .Iaddend..Iadd.25. The pair of non-inverted and inverted packaged semiconductor devices of claim 24 wherein the resin bodies of the inverted and non-inverted packaged semiconductor devices are substantially rectangular and the outer lead portions extend from opposite sides of each of the inverted and non-inverted packaged semiconductor devices. .Iaddend.