Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process

Abstract

A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N- epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

We claim: 
     
       1. Process for manufacturing an integrated .Iadd.structure comprising a .Iaddend.high-voltage bipolar power transistor and .Iadd.a .Iaddend.vertical low-voltage MOS power transistor . .structure.!., in . .the.!. .Iadd.an .Iaddend.emitter switching configuration, . .of the type in which: a.!. .Iadd.having an N- type .Iaddend.first . .high resistivity N- type.!. epitaxial layer, designed to form . .the.!. .Iadd.a .Iaddend.collector of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, . .is.!. grown on . .a.!. .Iadd.an .Iaddend.N+ type substrate, a P+ conductivity region, designed to serve as . .the.!. .Iadd.a .Iaddend.base of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, and . .then.!. an N+ type region, designed to serve as . .the.!. .Iadd.a .Iaddend.buried emitter . .zone.!. of . .the same.!. .Iadd.said bipolar power .Iaddend.transistor, . .are subsequently.!. created on said first .Iadd.epitaxial .Iaddend.layer, by deposition or . .implanation.!. .Iadd.implantation .Iaddend.and . .subsequent.!. diffusion, . .characterized by the fact that.!. .Iadd.said process comprising.Iaddend.:   a second N conductivity epitaxial layer, designed to constitute . .the.!. .Iadd.a .Iaddend.drain . .region.!. of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor and . .at the same time automaticaly.!. .Iadd.automatically .Iaddend.form . .the.!. .Iadd.a .Iaddend.connection between . .the.!. .Iadd.said .Iaddend.drain of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor and . .the.!. .Iadd.said buried .Iaddend.emitter of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, is grown on . .the.!. .Iadd.said .Iaddend.first epitaxial layer, . .the.!. .Iadd.a .Iaddend.body, . .the.!. .Iadd.a .Iaddend.source and . .the.!. .Iadd.a .Iaddend.gate of . .the.!. .Iadd.said .Iaddend.MOS .Iadd.power .Iaddend.transistor are . .then.!. created in . .the.!. .Iadd.said .Iaddend.second epitaxial layer, in correspondence with . .the aforesaid.!. .Iadd.said .Iaddend.buried emitter . .zone.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor,   a P+ type region, which enables . .the.!. .Iadd.electrical connection to be made to said .Iaddend.base . .region.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor . .to be electrically connected on the surface.!., is . .also.!. created at the side of . .the.!. said MOS .Iadd.power .Iaddend.transistor.   
     
     
       2. Process for manufacturing an integrated .Iadd.structure comprising a .Iaddend.high-voltage bipolar power transistor and .Iadd.a .Iaddend.horizontal low-voltage MOS power transistor . .structure.!., in . .the.!. .Iadd.an .Iaddend.emitter switching configuration, . .of the type in which: a high resistivity.!. .Iadd.having an .Iaddend.N- type epitaxial layer, designed to form . .the.!. .Iadd.a .Iaddend.collector of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, . .is.!. grown on an N+ type substrate, a first P+ type region . .is then created.!. in said epitaxial layer, a third N+ type region, designed to constitute . .the.!. .Iadd.an .Iaddend.emitter . .region.!. of . .the same.!. .Iadd.said bipolar power .Iaddend.transistor, . .is then created.!. .Iadd.and .Iaddend.within . .the aforesaid.!. .Iadd.said .Iaddend.first .Iadd.P+ type .Iaddend.region, .Iadd.said first P+ type region being .Iaddend.designed to constitute . .the.!. .Iadd.a .Iaddend.base of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor, .Iadd.said process being .Iaddend.characterized by the fact that:   a second P+ type region, separated from . .the.!. .Iadd.said .Iaddend.first .Iadd.P+ type region .Iaddend.by a region of . .the.!. .Iadd.said .Iaddend.epitaxial layer, is created in . .the.!. .Iadd.said .Iaddend.epitaxial layer simultaneously . .to.!. .Iadd.with .Iaddend.said first region,   a fourth .Iadd.N+ type region .Iaddend.and a fifth N+ type region, designed to constitute . .the MOS.!. .Iadd.a .Iaddend.source and .Iadd.a .Iaddend.drain . .region.!. respectively .Iadd.of said MOS power transistor.Iaddend., are created within . .the.!. .Iadd.said .Iaddend.second .Iadd.P+ type .Iaddend.region, the deposition of tracks of conductor material designed to electrically interconnect . .the.!. .Iadd.said .Iaddend.emitter and .Iadd.said .Iaddend.drain . .metal coatings.!. .Iadd.to each other .Iaddend.is carried out simultaneously . .to.!. .Iadd.with .Iaddend.the deposition of . .the.!. films of conductor material designed to form . .the.!. gate terminals and . .the meatal.!. .Iadd.metal .Iaddend.coatings which ensure the ohmic contact with . .the MOS.!. .Iadd.said .Iaddend.source and .Iadd.said .Iaddend.drain . .regions.!. .Iadd.of said MOS power transistor .Iaddend.and with . .the.!. .Iadd.said .Iaddend.base and emitter . .regions.!. of . .the.!. .Iadd.said .Iaddend.bipolar .Iadd.power .Iaddend.transistor.Iadd.;   wherein said MOS power transistor controllably cuts off current to said emitter of said bipolar power transistor, to provide high-voltage switching in a switched-emitter configuration having a primary current path between said fourth N+ type region and said N+ type substrate.Iaddend.. .Iadd.3. The method of claim 1, wherein said body of said MOS power transistor is formed before said source of said MOS power transistor. .Iaddend..Iadd.4. The method of claim 1, wherein said body and said source of said MOS power transistor are both formed by implantation. .Iaddend..Iadd.5. A process for manufacturing an integrated high-voltage bipolar power transistor and a vertical low-voltage MOS power transistor structure, comprising the steps of:   a) growing an N- type first epitaxial layer on an N+ type substrate, said first epitaxial layer providing a collector of said bipolar power transistor;   b) creating on said first epitaxial layer a P+ conductivity region providing a base of said bipolar power transistor, and an N+ the region providing a buried emitter zone, by deposition or implantation and diffusion;   c) growing an N conductivity second epitaxial layer on said first epitaxial layer, and forming a body region therein;   d) creating, at an upper surface of said second epitaxial layer, a source region and a gate of said MOS power transistor structure, in vertical correspondence with said buried emitter zone of said bipolar power transistor,   e) creating a P+ type region at the side of said MOS power transistor structure, which enables said base of said bipolar power transistor to be   
     
     
        electrically connected on said upper surface. .Iaddend..Iadd.6.  The method of claim 5, wherein said second epitaxial layer is grown directly on said first epitaxial layer. .Iaddend..Iadd.7. The method of claim 5, wherein said base is formed before said buried emitter zone. .Iaddend..Iadd.8. The method of claim 5, wherein said body region is formed before said source. .Iaddend..Iadd.9. The method of claim 5, wherein said body region and said source region are both formed by implantation. .Iaddend..Iadd.10. The method of claim 5, wherein said gate is insulated on the underside thereof. .Iaddend..Iadd.11. A process for manufacturing a structure having an integrated high-voltage bipolar power transistor and horizontal low-voltage MOS power transistor in an emitter switching configuration said process comprising the steps of: growing an N- type epitaxial layer, designed to form a collector of said bipolar power transistor, on an N+ type substrate,   creating in said epitaxial layer,   a first P+ type region, to constitute a base of said bipolar power transistor, and   a second P+ type region separated from said first P+ type region by a region of said epitaxial layer;   creating a third N+ type region, to constitute an emitter region of said bipolar power transistor, within said first P+ type region;   creating a fourth and a fifth N+ type region, to constitute a source region and a drain region respectively, of said MOS power transistor within said second P+ type region,   forming a thin film of conductor material which is positioned and operatively connected to provide a field-effect-transistor-gate which controls conduction between said source region and said drain region of said MOS power transistor, and   forming a strip of thin film conductor material which is positioned and operatively connected to electrically interconnect said emitter region of said bipolar power transistor and said drain region of said MOS power transistor;   wherein said MOS power transistor controllably cuts off current to said emitter of said bipolar power transistor, to provide high-voltage switching in a switched-emitter configuration having a primary current path between said source region of said MOS power transistor and said   
     
     
        collector of said bipolar power transistor. .Iaddend..Iadd.12.  The method of claim 11, wherein said field-effect-transistor-gate is insulated on the underside thereof. .Iaddend..Iadd.13. A process for manufacturing a microelectronic structure which includes a vertical high-voltage bipolar power transistor, and which also includes a vertical low-voltage MOS power transistor structure extending to a front surface thereof, comprising the steps of: a) on an N+ type substrate, growing an N- type first epitaxial layer, to provide the collector of the bipolar power transistor;   b) creating, near the front surface of said first epitaxial layer, a P+ region to provide a base of said bipolar power transistor, and an N+ type region, which is shallower than said P+ region, to provide an emitter of said bipolar power transistor;   c) growing an N+ type additional epitaxial layer above said first epitaxial layer;   d) forming, in said additional epitaxial layer, a P- type body region, and an N- type source region which is shallower than said body region, and a P+ sinker region which provides ohmic contact to said base; and   e) creating, atop said additional epitaxial layer, an insulated gate electrode which is capacitively coupled to at least some potions of said body which are laterally adjacent to said source region. .Iaddend..Iadd.14. The method of claim 13, wherein said additional epitaxial layer is grown directly on said first epitaxial layer. .Iaddend..Iadd.15. The method of claim 13, wherein said base is formed before said emitter. .Iaddend..Iadd.16. The method of claim 13, wherein said body region is formed before said source region. .Iaddend..Iadd.17. The method of claim 13, wherein said body and source regions are both   
     
     
        formed by implantation. .Iaddend..Iadd.18.  The method of claim 13, wherein said gate electrode is insulated on the underside thereof. .Iaddend..Iadd.19. A process for manufacturing a solid-state structure which includes an integrated high-voltage bipolar power transistor, and which also includes a vertical low-voltage MOS power transistor, comprising the steps of: a) providing a monolithic semiconductor structure which includes a first region which is doped with a dopant of a first conductivity type and a second region of said first conductivity type and is more lightly doped than said first region, and providing a metallic backside contact to said first region;   b) creating, in an upper surface of said monolithic semiconductor structure, a third region which is doped with a second conductivity type that is opposite to said first conductivity type, and a fourth region which is doped with said first conductivity type;   c) epitaxially growing an additional layer of semiconductor material of said first conductivity type above said monolithic semiconductor structure;   d) forming, in proximity to said front surface, a body diffusion of said second conductivity type, and   a source diffusion of said first conductivity type that is completely separated by said body diffusion from other portions of said additional layer of semiconductor material, and   a diffusion region of said second conductivity type which extends upward from said third region;     e) creating, atop said additional layer of semiconductor material, an insulated gate electrode which is capacitively coupled to portions of said body diffusion which are laterally adjacent to said source diffusion. .Iaddend..Iadd.20. The method of claim 19, wherein said body diffusion is formed before said source diffusion. .Iaddend..Iadd.21. The method of claim 19, wherein said body and source diffusions are both formed by implantation. .Iaddend..Iadd.22. The method of claim 19, wherein said gate electrode is insulated on the underside thereof. .Iaddend..Iadd.23. The method of claim 19, wherein said additional layer is grown directly on said monolithic semiconductor structure. .Iaddend..Iadd.24. The method of claim 19, wherein said first region of said monolithic semiconductor structure is a substrate, and said second region is an epitaxial layer grown on said substrate. .Iaddend..Iadd.25. The method of claim 19, wherein said first conductivity type is N- type. .Iaddend.