Directly bonded SIMM module

Abstract

A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board. The encapsulated chips will replace both the leadframe and printed circuit board (electrical only) as we now know it in the conventional SIMM module.

We claim: 
     
       1. A memory array in which a plurality of memory circuit devices are arranged in a manner such that memory information is obtained by addressing bits of information from a selected number of the memory devices in the array in a format, and the format of bits forms a byte of memory data such that each byte includes bits from each memory device in the selected number of the circuit devices, and wherein the bits are addressed as rows and columns of information in a matrix on each memory device, characterized by: (a) a support structure which includes a single polymeric sheet, the polymeric sheet having a plurality of die receiving portions thereon, having tape automated bond (TAB) leads thereon and having a first set of electrical circuit traces on one side of the polymeric sheet, the tape automated bond pads being in electrical communication with the circuit traces;   (b) a plurality of integrated circuitry memory devices, each device consisting of circuit elements deposited on a substrate and having conductive bumps deposited thereon, the integrated circuit devices being located within separate ones of the receiving portions of the single polymeric sheet, and connected to the polymeric sheet by being attached to the tape automated bond pads at the conductive bumps, and each of the integrated circuit devices being connected to the TAB leads on the polymeric sheet within its respective die receiving portion;   (c) a second set of circuit traces on a plane which is separate from said one side of the polymeric sheet, the second set of circuit traces being in electrical communication with the first set of electrical circuit traces;   (d) circuit terminals in electrical communication with the circuit traces, the circuit terminals configured in a pattern which conforms to a predetermined external circuit connection and memory address protocol; and   (e) means to mechanically stabilize the memory array so that the polymeric sheet, the memory devices and the circuit terminals are maintained in electrical communication during normal service.   
     
     
       2. A memory array as defined in claim 1, further characterized by: the means to mechanically stabilize the memory array including mechanical structure which supports the circuit terminals.   
     
     
       3. A memory array as defined in claim 2, further characterized by: the means to mechanically stabilize the memory array including plastic encapsulation of the polymeric sheet and the memory devices.   
     
     
       4. A memory array as defined in claim 2, further characterized by: the means to mechanically stabilize the memory array including plastic encapsulation of the polymeric sheet and the memory devices, wherein the circuit terminals remain at lest partially exposed through the encapsulation.   
     
     
       5. A memory array as defined in claim 2, further characterized by: the circuit terminals conforming to a SIP pin configuration.   
     
     
       6. A memory array as described in claim 1, characterized by: the terminals being configured as a SIMM edge connector, wherein the edge connector is insertable into a data bus slot for SIMM configuration memory modules.   
     
     
       7. A memory array as described in claim 1, characterized by: (a) the second set of circuit traces having tape automated bond (TAB) pads thereon, the tape automated bond pads being in electrical communication with the circuit traces on the polymeric sheet;   (b) a second plurality of integrated circuit memory devices, each device consisting of circuit elements deposited on a substrate and having conductive bumps deposited thereon, the integrated circuit devices being attached to the tape automated bond pads on the second set of circuit traces at the conductive bumps; and   (c) said means to mechanically stabilize the memory array further supporting the second plurality of integrated circuit memory devices.   
     
     
       8. A memory array as described in claim 1, characterized by: (a) each memory device having addresses which are arranged in similar matrices of rows and columns on the memory device; and   (b) the addressing of a row of memory devices being accomplished to corresponding rows and columns on each memory device in a row of memory devices in response to address commands.   
     
     
       9. A memory array as described in claim 1, further characterized by: one of said memory devices in each row providing parity information such that a column of the memory devices provides said parity information.   
     
     
       10. A memory array as described in claim 1, further characterized by: (a) the memory devices being random access memory semiconductor devices, having read and write address bits thereon;   (b) the devices having row and column enable bits for the memory devices.   
     
     
       11. A memory array as described in claim 1, further characterized by: the memory devices being dynamic random access memories.   
     
     
       12. A memory array as described in claim 1, further characterized by: (a) an address circuit responding to address signals received from a computer and addressing the memory devices in a sequence which permits said selective enablement; and   (b) said address circuit being a programmable array logic circuit, the programmable array logic device controlling the enablement of memory devices in said memory array.   
     
     
       13. A memory array as described in claim 1, further characterized by: (a) each memory device having addresses which are arranged in similar matrices of rows and columns on the memory device;   (b) the addressing of a row of memory devices being accomplished to corresponding rows and columns on each memory device in a row of memory devices in response to address commands;   (c) an address circuit responding to address signals received from a computer and addressing the memory devices in a sequence which permits said selective enablement;   (d) a driver for providing address signals to said address circuit, in response to signals received from the computer; and   (e) termination capacitors used to compensate for a shifted impedance load of the memory devices caused by the multiple rows of said memory devices, when provided with computer address signals at signal levels intended for a single row of memory devices.