Dynamic random access memory device with the combined open/folded bit-line pair arrangement

Abstract

A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a substrate;   a plurality of word lines on said substrate;   a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups;   an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines, and said array of memory cells being divided into a plurality of subarray sections in a direction along the bit lines;   a plurality of sense amplifiers each connected between two of said bit line groups which are adjacent to each other in the row direction along the bit lines, said sense amplifiers including a first sense amplifier connected to two of said bit lines of one of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged adjacent to said first sense amplifier and connected between said one of said bit line groups and the other which is neighboring thereto, in an open bit-line scheme;   a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said bit line groups which is arranged between said first and second sense amplifiers and two second switching circuits, one connected between said second sense amplifier and one of said adjacent two bit line groups and the other between said second sense amplifier and the other of said adjacent two bit line groups, and first switching circuit including switching elements connected to .[.the three.]. .Iadd.four .Iaddend.bit lines of one of said bit line groups and driven to connect said first sense amplifier to the bit lines of said one of said bit line groups in the folded bit-line scheme, and each of said second switching circuits including .[.three.]. .Iadd.two .Iaddend.switching elements connected to .[.the three.]. .Iadd.two .Iaddend.bit lines of one of said bit line groups and driven to connect the bit lines of said adjacent two bit line groups to said second sense amplifier in the open bit-line scheme.   
     
     
       2. A semiconductor memory device according to claim 1, wherein said bit lines includes first and second bit line pairs, said first switching means includes first and second switching element pairs, two switching elements of one of said pairs having first terminals connected respectively to adjacent two of said bit lines and second terminals connected to each other and a first terminal of said first sense amplifier, and two switching elements of the other of said pairs having first terminals connected respectively to adjacent two of said bit lines and second terminals connected to each other and a second terminal of said first sense amplifier. 
     
     
       3. A semiconductor memory device according to claim 1, wherein said bit lines include first and second bit line pairs between which said second sense amplifier is arranged, said second switching means includes first and second switching element pairs, two switching elements of one of said pairs having first terminals connected respectively to adjacent two of said bit lines and second terminals connected to each other and a first terminal of said second sense amplifier, and two switching elements of the other of said pairs having first terminals connected respectively to adjacent two of said bit lines and second terminals connected to each other and a second terminal of said second sense amplifier. 
     
     
       4. A semiconductor memory device according to claim 1, wherein said sense amplifiers include a plurality of first sense amplifier and a plurality of second sense amplifiers, each of said second sense amplifiers being arranged between adjacent two of said first sense amplifiers; said subarray sections includes a first subarray section arranged between one of said second sense amplifiers and one of said first sense amplifiers and a second subarray section arranged between said one of said second sense amplifiers and another of said first sense amplifiers;   said bit lines includes first to fourth bit lines extending between one of said second sense amplifiers and one of said first sense amplifiers and fifth to eighth bit lines extending between said one of said second sense amplifiers and another one of said first sense amplifiers;   said first switching means includes first and second switching element pairs, two switching elements of one of said pairs having first terminals connected respectively to said first and second bit lines and second terminals connected to each other and a first terminal of said first sense amplifier and two switching elements of the other of said pairs having first terminals connected respectively to said third and fourth bit lines and second terminals connected to each other and a second terminal of said first sense amplifier;   said second switching means includes third and fourth switching element pairs, two switching elements of one of said pairs having first terminals connected respectively to said second and third bit lines and second terminals connected to each other and a first terminal of said second sense amplifier and two switching elements of the other of said pairs having first terminals connected respectively to said sixth and seventh bit lines and second terminals connected to each other and a second terminal of said second sense amplifier.   
     
     
       5. A semiconductor memory device according to claim 1, further comprising a binary to ternary conversion logic circuit for receiving an input binary number consisting of a plurality of digits and generating a remainder obtained by when said input binary number is divided by three as a control signal supplied to said switching section, to selectively connect said sense amplifiers to said bit lines in the folded bit-line scheme and the open bit-line scheme. 
     
     
       6. A semiconductor memory device according to claim 5, wherein said logic circuit comprises: .Iadd.data transfer means for subdividing the input binary number into a plurality of subdivided units each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number;   first circuit means .[.for subdividing the input binary number into a plurality of sections each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number.].; .Iadd.consisting of circuits for each receiving a signal from each of the plurality of subdivided units as being the least significant bit for each circuit and for each generating a remainder obtained divided by three; .Iaddend.and   second circuit means connected to said first circuit, for generating a least significant digit of a ternary number which is obtained by adding together outputs of said first circuit means.   
     
     
       7. A semiconductor memory device comprising: a substrate;   a plurality of word lines on said substrate;   a plurality of bit lines transverse to said word lines on said substrate;   an array of memory calls selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines, and said array of memory cells being divided into a plurality of subarray sections in the row direction along the bit lines; and   a plurality of sense amplifiers each connected between adjacent two of said subarray sections and to said bit lines, adjacent two of said sense amplifiers operating, in a reading mode, in a folded bit-line scheme, and in a writing mode, in a folded bit-line scheme and an open bit-line scheme, respectively. .[.8. A semiconductor memory device according to claim 7, wherein said bit lines are divided into a plurality of bit line groups each having a plurality of bit lines, with each of said sense amplifiers being arranged between adjacent two of said bit line groups; and which includes first switching means connected between one of said bit line groups and one of said sense amplifiers, and second switching means connected between said one of said bit line groups and another of said sense amplifiers, said first and second switching means being operated so as to connect the bit lines of said bit line groups to said adjacent two of said sense amplifiers in the folded bit-line scheme and open bit-line   
     
     
        scheme..].9. A semiconductor memory device according to claim 7, wherein said bit lines are divided into a plurality of bit line groups having first and second bit line groups, with said sense amplifiers including a first sense amplifier arranged .[.between said first and second bit line groups and a second sense amplifier arranged between said second bit line group and another line group.]..Iadd.adjacent to said first bit line group.Iaddend., and said semiconductor memory device including first switching means connected between said first bit line group and .[.said sense amplifier.]..Iadd.said first sense amplifier.Iaddend., second switching means connected between said .[.second.]. .Iadd.first .Iaddend.bit line group and .[.said sense amplifier.]..Iadd.said second sense amplifier.Iaddend., and third switching means connected between said second bit line group and said second sense amplifier, said first to third switching means being ON/OFF-controlled to operate said first and second sense amplifiers in a folded bit-line scheme in the reading mode and to operate them in a folded bit-line scheme and an open bit-line scheme in the writing mode,   
     
     
        respectively. 10. A semiconductor memory device according to claim 7, further comprising a binary to ternary conversion logic circuit for receiving an input binary number consisting of a plurality of digits and generating a remainder obtained by when said input binary number is divided by three as a control signal supplied to said switching section, to selectively connect said sense amplifiers to said bit lines in the 
     
     
        folded bit-line scheme and the open bit-line scheme. 11. A semiconductor memory device according to claim 10, wherein said logic circuit comprises: first circuit means for subdividing the input binary number into a plurality of sections each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number; and   second circuit means connected to said first circuit, for generating a least significant digit of a ternary number which is obtained by adding   
     
     
        together outputs of said first circuit means. 12. A semiconductor memory device comprising: a substrate;   a plurality of word lines on said substrate; a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups having three bit lines;   an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in a column direction along the word lines while said memory cells are arranged at all cross points along a center one of the three bit lines of each of said bit line groups, and said array of memory cells being divided into a plurality of subarray sections in a row direction of the bit lines; and   a plurality of sense amplifiers each connected between adjacent two of said subarray sections, said sense amplifiers including a first sense amplifier connected to two of said bit lines of each of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged adjacent to said first sense amplifier and between adjacent two of said bit line groups and connected to a center one of the bit lines of each of the adjacent two bit line groups in an open bit-line scheme, said first sense amplifier being operated in a folded bit-line scheme while said second sense amplifier is operated in an open bit-line scheme. .[.13. A semiconductor memory device according to claim 12, further comprising a binary to ternary conversion logic circuit for receiving an input binary number consisting of a plurality of digits and generating a remainder obtained by when said input binary number is divided by three as a control signal supplied to said switching section, to selectively connect said sense amplifiers to said bit lines in the folded bit-line scheme and the open bit-line scheme..]..[.14. A semiconductor memory device according to claim 13, wherein said logic circuit comprises:   first circuit means for subdividing the input binary number into a plurality of sections each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number; and second circuit means connected to said first circuit, for generating a least significant digit of a ternary number which is obtained by adding together   
     
     
        outputs of said first circuit mean..].15. A semiconductor memory device comprising: a substrate;   a plurality of word lines on said substrate;   a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups each having three bit lines;   an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines and said array of memory cells being divided into a plurality of subarray sections in a row direction along the bit lines; and   a plurality of sense amplifiers each connected between adjacent two of said bit line groups in the row direction along the bit lines, said sense amplifiers including a first sense amplifier connected to two of said three bit lines of each of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged neighboring to said first sense amplifier and connected between two of said bit line groups, which are adjacent to each other in the row direction of the bit lines, in an open bit-line scheme, thereto, in an open bit line scheme; and   a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said bit line groups which is adjacent to said second sense amplifier and two second switching circuits connected, respectively, between said second sense amplifier and said adjacent two bit line groups, said first switching circuit including three switching elements connected respectively to the three bit lines of one of said bit line groups and driven to connect said first sense amplifier to the bit lines of said one of said bit line groups in the folded bit-line scheme, and each of said second switching circuits including three switching elements connected to the three bit lines of one of said bit line groups and driven to connect the bit lines of said adjacent two bit line groups to said second sense amplifier in the open   
     
     
        bit-line scheme. 16. A semiconductor memory device according to claim 15, wherein the three switching elements of said first switching circuit include first and second switching elements each connected between a corresponding one of the three bit lines and a first terminal of said first sense amplifier and a third switching element connected between a corresponding one of the three bit lines and a second terminal of said first sense amplifier, and the three switching elements of one of said second switching circuits include fourth and fifth switching elements each connected between a corresponding one of the three bit lines and a first terminal of said second sense amplifier and a sixth switching element connected between a corresponding one of the three bit lines and a second terminal of said second sense amplifier, and the three switching elements of the other of said second switching circuits include seventh and eighth switching elements each connected between a corresponding one of the three bit lines and the second terminal of said second sense amplifier and a ninth switching element connected between a corresponding one of the three 
     
     
        bit lines and the first terminal of said second sense amplifier. 17. A semiconductor memory device according to claim 15, further comprising a binary to ternary conversion logic circuit for receiving an input binary number consisting of a plurality of digits and generating a remainder obtained by when said input binary number is divided by three as a control signal, supplied to said switching section, to selectively connect said sense amplifiers to said bit lines in the folded bit-line scheme and the 
     
     
        open bit-line scheme. 18. A semiconductor memory device according to claim 17, where in said logic circuit comprises: first circuit means for subdividing the input binary number into a plurality of sections each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number; and   second circuit means connected to said first circuit, for generating a least significant digit of a ternary number which is obtained by adding   
     
     
        together outputs of said first circuit means. 19. A semiconductor memory device comprising: a substrate;   a plurality of word lines on said substrate; a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups;   an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines, and said array of memory cells being divided into a plurality of subarray sections in the row direction along the bit lines;   a plurality of sense amplifiers each connected between two of said bit line groups which are adjacent to each other in the row direction along the bit lines, said sense amplifiers including a first sense amplifier connected to two of said bit lines of one of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged adjacent to said first sense amplifier and connected direction along said word lines and connected between said one of said bit line groups and the other which is neighboring thereto, in an open bit-line scheme; and   a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said bit line groups which is arranged between said first and second sense amplifiers and two second switching circuits, one connected between said second sense amplifier and one of said adjacent two bit line groups and the other between said second sense amplifier and the other of said adjacent two bit line groups, and first switching circuit including switching elements connected respectively to the three bit lines of one of said bit line groups and driven to connect said first sense amplifier to the bit lines of said one of said bit line groups in the folded bit-line scheme, and each of said second switching circuits including three switching elements connected respectively to the three bit lines of one of said bit line groups and driven to connect the bit lines of said adjacent two bit line   
     
     
        groups to said second sense amplifier in the open bit-line scheme. 20. A semiconductor memory device according to claim 19, further comprising a binary to ternary conversion logic circuit for receiving an input binary number consisting of a plurality of digits and generating a remainder obtained by when said input binary number is divided by three as a control signal supplied to said switching section, to selectively connect said sense amplifiers to said bit lines in the folded bit-line scheme and the 
     
     
        open bit-line scheme. 21. A semiconductor memory device according to claim 20, wherein said logic circuit comprises: first circuit means for subdividing the input binary number into a plurality of sections each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number; and   second circuit means connected to said first circuit, for generating a least significant digit of a tern @ number which is obtained by adding   
     
     
        together outputs of said first circuit means. 22. A semiconductor memory device comprising: a substrate;   a plurality of word lines on said substrate;   a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups in a direction along the bit lines .[.and.]. each of said bit line groups.[., said bit lines.]. including a plurality of folded bit-line pairs and a plurality of .[.bit-line pairs and each of the.]. bit lines .Iadd.each .Iaddend.belonging to each of .[.said.]. .Iadd.a plurality of .Iaddend.open bit-line pairs being arranged to extend in a zig-zag manner between two bit lines of said folded bit-line pairs .Iadd.and between said folded bit-line pairs.Iaddend.;   an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, said memory cells including a plurality of memory cells arranged along said folded-bit line pairs at every other cross point and a plurality of memory cells arranged at all cross points along said open bit-line pairs, and said array of memory cells being divided into a plurality of subarray sections in a row direction along the bit lines;   a plurality of sense amplifiers each connected between two of said bit line groups which are adjacent to each other in the row direction along the bit lines, said sense amplifiers including a first sense amplifiers connected to said folded bit-line pairs of one of said bit line groups in a folded bit-line scheme and two second sense amplifiers arranged in the column direction along said word lines, each of said second sense amplifiers being connected between said one of said bit line groups and the other which is neighboring thereto, in an open bit-line scheme; and   a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said folded bit-line pairs and a second switching circuit connected between said second sense amplifier and one of said open bit-line pairs. .[.23. A semiconductor memory device according to claim 22, further comprising a binary to ternary conversion logic circuit for receiving an input binary number consisting of a plurality of digits and generating a remainder obtained by when said input binary number is divided by three as a control signal supplied to said switching section, to selectively connect said sense amplifiers to said bit lines in the folded bit-line scheme and the open bit-line scheme..]..[.24. A semiconductor memory device according to claim 23, wherein said logic circuit comprises:   first circuit means for subdividing the input binary number into a plurality of sections each having a predetermined number of digits being as a unit, said unit being sequentially defined by counting up the digits from a least significant digit of said input binary number; and   second circuit means connected to said first circuit, for generating a least significant digit of a ternary number which is obtained by adding together outputs of said first circuit means..].