High speed configuration independent programmable macrocell

Abstract

A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

What is claimed is:  
     
       1. A circuit comprising: 
       a plurality of user configurable inputs for configuring said circuit;  
       clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs;  
       a switching element including at least one pass gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said pass gate; and  
       a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.  
     
     
       2. The circuit as set forth in  claim 1 , wherein said data path circuit comprises a register. 
     
     
       3. The circuit as set forth in  claim 1 , wherein said data path circuit comprises a combinatorial circuit. 
     
     
       4. The circuit as set forth in  claim 1 , wherein said logic function implemented in said clock logic comprises a multiplexer function. 
     
     
       5. The circuit as set forth in  claim 1 , wherein said logic function implemented in said clock logic comprises a decoder function. 
     
     
       6. The circuit as set forth in  claim 4 , wherein said multiplexer function comprises multiplexing between a D-type register, T-type register and a latch. 
     
     
       7. The circuit as set forth in  claim 1 , wherein said logic function, implemented in said clock logic, comprises a polarity function for generating a true or a bar output for said circuit. 
     
     
       8. The circuit as set forth in  claim 1 , wherein: 
       said user configurable inputs comprise a D-type register select, a T-type resister select, a latch select and a polarity select;  
       said logic function implemented in said clock logic comprises a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, said logic function comprises a toggle function for implementing a T-type flip-flop, and said logic function comprises a polarity function for generating a true or a bar output for said circuit; and  
       said data path circuit comprises a master latch, coupled to receive said logic output, and a slave latch coupling said master latch and said circuit output.  
     
     
       9. The circuit as set forth in  claim 8 , wherein said switching element comprises: 
       a three state inverter coupled to said input signal and being controlled by said clock logic for inverting said input data in accordance with said D-type register select, said T-type resister select, and said polarity select; and  
       a transmission gate coupled to said input signal and being controlled by said clock logic for passing said input data in accordance with said D-type register select, said T-type resister select, and said polarity select.  
     
     
       10. A programmable logic device (PLD) comprising: 
       a plurality of user configurable inputs for configuring said PLD; at least one macrocell, coupled to receive said user configurable inputs, said macrocell comprising:  
       clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs;  
       a switching element including at least one transmission gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and  
       a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.  
     
     
       11. The programmable logic device as set forth in  claim 10 , wherein said data path circuit comprises a register. 
     
     
       12. The programmable logic device as set forth in  claim 10 , wherein said data path circuit comprises a combinatorial circuit. 
     
     
       13. The programmable logic device as set forth in  claim 10 , wherein said logic function implemented in said clock logic comprises a multiplexer function. 
     
     
       14. The programmable logic device as set forth in  claim 10 , wherein said logic function implemented in said clock logic comprises a decoder function. 
     
     
       15. The programmable logic device as set forth in  claim 11 , wherein said multiplexer function comprises multiplexing between a D-type register, T-type register and a latch. 
     
     
       16. The programmable logic device as set forth in  claim 10 , wherein said logic function, implemented in said clock logic, comprises a polarity function for generating a true or a bar output for said circuit. 
     
     
       17. The programmable logic device as set forth in  claim 10 , wherein: 
       said user configurable inputs comprise a D-type register select, a T-type resister select, a latch select and a polarity select;  
       said logic function implemented in said clock logic comprises a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, said logic function comprises a toggle function for implementing a T-type flip-flop, and said logic function comprises a polarity function for generating a true or a bar output for said circuit; and  
       said data path circuit comprises a master latch, coupled to receive said logic output, and a slave latch coupling said master latch and said circuit output.  
     
     
       18. The programmable logic device as set forth in  claim 17 , wherein said switching element comprises: 
       a three state inverter coupled to said input signal and being controlled by said clock logic for inverting said input data in accordance with said D-type register select, said T-type resister select, and said polarity select; and  
       a transmission gate coupled to said input signal and being controlled by said clock logic for passing said input data in accordance with said D-type register select, said T-type resister select, and said polarity select.  
     
     
       19. A method for configuring a circuit comprising the steps of: 
       receiving a plurality of user configurable inputs for configuring said circuit;  
       receiving a clock input;  
       generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs;  
       receiving an input signal for said circuit in a switching element including at least one pass gate;  
       receiving some of said conditional clock signals in said switching element;  
       generating a logic output from said switching element, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and  
       providing a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.  
     
     
       20. A circuit comprising: 
       
         a plurality of configurable inputs;  
       
       
         clock logic generating a plurality of conditional clock signals in response to a clock input and the configurable inputs, the conditional clock signals implementing a logic function;  
       
       
         a pass gate controlling propagation of an input signal and generating a logic output in accordance with at least one of the conditional clock signals; and  
       
         a data path circuit receiving  ( i )  the logic output of the pass gate and  ( ii )  at least one of the remaining conditional clock signals, the data path circuit providing additional functionality.   
     
     
       21. The circuit of  claim 20 , wherein the data path circuit comprises a register. 
     
     
       22. The circuit of  claim 20 , wherein the data path circuit comprises a D- type flip - flop, a T - type flip - flop or a latch.   
     
     
       23. The circuit of  claim 22 , further comprising set/reset logic having an output coupled to an input of the D- type flip - flop, the T - type flip - flop or the latch.   
     
     
       24. The circuit of  claim 20 , wherein the data path circuit comprises a D- type flip - flop.   
     
     
       25. The circuit of  claim 24 , further comprising set/reset logic having an output coupled to an input of the D- type flip - flop.   
     
     
       26. The circuit of  claim 20 , wherein the data path circuit comprises a combinatorial circuit. 
     
     
       27. The circuit of  claim 20 , wherein the data path circuit comprises a static random access memory cell. 
     
     
       28. The circuit of  claim 20 , wherein the data path circuit comprises a three state buffer. 
     
     
       29. The circuit of  claim 20 , wherein the logic function comprises a multiplexer function. 
     
     
       30. The circuit of  claim 20 , wherein the logic function comprises a decoder function. 
     
     
       31. The circuit of  claim 30 , wherein the configurable inputs comprise bits in a static random access memory. 
     
     
       32. The circuit of  claim 30 , wherein the configurable inputs comprise a polarity select bit. 
     
     
       33. The circuit of  claim 30 , wherein the configurable inputs comprise one or more function select bits. 
     
     
       34. The circuit of  claim 20 , wherein the logic function comprises a polarity function generating a true output and a complementary output. 
     
     
       35. The circuit of  claim 20 , wherein the configurable inputs comprise bits in a shift register, a static random access memory or an electrically erasable and programmable read only memory. 
     
     
       36. The circuit of  claim 20 , wherein the additional functionality comprises a flip- flop function.   
     
     
       37. The circuit of  claim 20 , further comprising a feedback loop connecting an output of said data path circuit to an input of said clock logic. 
     
     
       38. A programmable logic device, comprising: 
       
         a plurality of configurable inputs;  
       
       
         clock logic generating a plurality of conditional clock signals in response to a clock input and the configurable inputs, the conditional clock signals implementing a logic function;  
       
       
         a pass gate controlling propagation of an input signal and generating a logic output in accordance with at least one of the conditional clock signals; and  
       
         a data path circuit receiving  ( i )  the logic output of the pass gate and  ( ii )  at least one of the remaining conditional clock signals, the data path circuit providing additional functionality.   
     
     
       39. The device of  claim 38 , wherein the propagation is independent of the configurable inputs. 
     
     
       40. A method for configuring a circuit, comprising the steps of: 
       ( a )  generating a set of conditional clock signals in response to a clock input and a plurality of configurable inputs;    
       ( b )  implementing a logic function at a switch comprising at least one pass gate, said switch receiving an input signal;    
       ( c )  generating a logic output from the switch in accordance with at least one of the conditional clock signals; and    
       ( d )  controlling propagation of the input signal through the switch in accordance with at least one of the conditional clock signals.   
     
     
       41. The method of  claim 40 , wherein the propagation is independent of the configurable inputs. 
     
     
       42. The method of  claim 41 , further comprising providing additional functionality from a data path receiving ( i )  the logic output and  ( ii )  at least one of the remaining conditional clock signals.