USRE39603EExpiredUtility

Process for manufacturing semiconductor device and semiconductor wafer

64
Assignee: NEC ELECTRONICS CORPPriority: Sep 30, 1994Filed: Aug 22, 2003Granted: May 1, 2007
Est. expirySep 30, 2014(expired)· nominal 20-yr term from priority
Inventors:Keiichiro KataShinichi Chikaki
H10W 72/922H10W 72/952H10W 72/923H10W 70/05H10W 72/012H10W 72/073H10W 72/251H10W 72/252H10W 72/244H10P 54/00H10W 72/019
64
PatentIndex Score
10
Cited by
35
References
22
Claims

Abstract

A process for manufacturing a semiconductor device includes defining chip sections on a wafer by scribe lines with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for on the chip electrodes. Aluminum interconnection layers are provided such that each layer is connected to the chip electrode at one end thereof and the other end of the layer is extended towards the central portion of the chip section. A cover coating film is applied on the passivating film and the layers. A number of apertures are formed in the coating film passing therethrough, and bump electrodes are formed at the position corresponding to the apertures. The chip sections are then separated from each other along the scribe lines into semiconductor devices.

Claims

exact text as granted — not AI-modified
1. A semiconductor wafer, including:
 a plurality of the sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including: 
 a plurality of chip electrodes positioned on said chip section; and  
 a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,  
 said bump electrodes being located at positions other than over said chip electrodes,  
 said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center.  
   
     
     
       2. A semiconductor wafer, including:
 a plurality of chip sections defined thereon by scribe lines, each chip section having 
 bump electrodes formed simultaneously thereon;  
 a plurality of chip electrodes positioned on said chip section; and  
 a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,  
 said bump electrodes being located at positions other than over said chip electrodes,  
 said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center.  
   
     
     
       3. A semiconductor wafer including:
 a plurality of chip sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including: 
 a plurality of chip electrodes positioned on said chip section; and  
 a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,  
 said bump electrodes being located at positions other than over said chip electrodes,  
 wherein each of said interconnection layers comprises an aluminum layer and a plating on said aluminum layer, wherein said aluminum layer and said plating extend from one of said bump electrodes to one of said chip electrodes and said plating contacts said one of said bump electrodes and said aluminum layer contacts said one of said chip electrodes.  
 
 
     
     
       4. A semiconductor wafer including:
 a plurality of chip sections defined thereon by scribe lines, each chip section having: 
 bump electrodes formed simultaneously thereon;  
 
 a plurality of chip electrodes positioned on said chip section; and  
 a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,  
 said bump electrodes being located at positions other than over said chip electrodes,  
 wherein each of said interconnection layers comprises an aluminum layer and a plating on said aluminum, wherein said aluminum layer and said plating extends from one said bump electrodes to one of said chip electrodes and said plating contacts said one of said bump electrodes and said aluminum layer contacts said one of said chip electrodes.  
 
     
     
       5. A semiconductor wafer as in  claim 3 , wherein said plating compromises  comprises  one of nickel and copper. 
     
     
       6. A semiconductor wafer as in  claim 3 , wherein said aluminum layer has a thickness of no greater than 1 micrometer. 
     
     
       7. A semiconductor wafer as in  claim 3 , wherein said plating has a thickness of at least 5 micrometers. 
     
     
       8. A semiconductor wafer as in  claim 3 , further comprising a gold layer between said bump electrode and said plating. 
     
     
       9. A semiconductor wafer as in claim  1    4 , wherein each of said chip sections has a center and a periphery and said interconnection layers extend from said periphery toward said center. 
     
     
       10. A semiconductor wafer as in  claim 4 , wherein said plating comprises one of nickel and copper. 
     
     
       11. A semiconductor wafer as in  claim 4 , wherein said aluminum layer has a thickness of no greater than 1 micrometer. 
     
     
       12. A semiconductor wafer as in  claim 4 , wherein said plating has a thickness of at least 5 micrometers. 
     
     
       13. The semiconductor wafer of  claim 3 , wherein each chip section has a center and a periphery and said interconnection layers extend from said periphery toward said center, and wherein the plurality of chip electrodes are positioned on said periphery. 
     
     
       14. The semiconductor wafer of  claim 4 , wherein each chip section has a center and a periphery and said interconnection layers extend from said periphery toward said center, and wherein the plurality of chip electrodes are positioned on said periphery. 
     
     
       15. A semiconductor wafer, including:
   a plurality of the sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including:      a plurality of chip electrodes positioned on said chip section; and        a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,          said bump electrodes being located at positions other than over said chip electrodes,        said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center,        wherein said bump electrodes are arranged in a grid array.     
     
     
       16. A semiconductor wafer, including:
   a plurality of chip sections defined theron by scribe lines,        each chip section having:      bump electrodes formed simultaneously theron; a plurality of chip electrodes positioned on said chip section; and        a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,          said bump electrodes being located at positions other than over said chip electrodes,        said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center,        wherein said bump electrodes are arranged in a grid array.     
     
     
       17. The semiconductor wafer of  claim 3 , wherein said bump electrodes are arranged in a grid array. 
     
     
       18. The semiconductor wafer of  claim 4 , wherein said bump electrodes are arranged in a grid array. 
     
     
       19. A semiconductor wafer, including:
   a plurality of the sections defined thereon by scribe lines, each chip section having bump electrodes formed simultaneously thereon, the scribe lines for separating the chip sections from each other without dividing bump electrodes thereon, said chip section including:      a plurality of chip electrodes positioned on said chip section; and        a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,          said bump electrodes being located at positions other than over said chip electrodes,        said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center,        wherein a pitch of said chip electrodes is different from a pitch of said bump electrodes.     
     
     
       20. A semiconductor wafer, including:
   a plurality of chip sections defined theron by scribe lines,        each chip section having:      bump electrodes formed simultaneously theron; a plurality of chip electrodes positioned on said chip section; and        a plurality of interconnection layers for electrically connecting said chip electrodes and said bump electrodes,          said bump electrodes being located at positions other than over said chip electrodes,        said chip section having a center and a periphery and said interconnection layers extend from said periphery toward said center,        wherein a pitch of said chip electrodes is different from a pitch of said bump electrodes.     
     
     
       21. The semiconductor wafer of  claim 3 , wherein a pitch of said chip electrodes is different from a pitch of said bump electrodes. 
     
     
       22. The semiconductor wafer of  claim 4 , wherein a pitch of said chip electrodes is different from a pitch of said bump electrodes.

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