P
USRE44251EExpiredUtilityPatentIndex 84

Circuit board for mounting electronic parts

Assignee: ASAI MOTOOPriority: Sep 12, 1996Filed: May 6, 2004Granted: Jun 4, 2013
Est. expirySep 12, 2016(expired)· nominal 20-yr term from priority
Inventors:ASAI MOTOOKAWAMURA YOICHIROMORI YOJI
H10W 90/724H10W 72/07251H10W 72/20H10W 70/655H10W 70/635H10W 70/611H10W 70/69H10W 70/65H10W 90/401H05K 2201/09509H05K 2201/09227H05K 1/0271H01R 12/523H05K 2201/09536H05K 3/184H05K 2201/10674H05K 2201/0212H05K 2201/09727H05K 2201/10734H05K 3/4602H05K 3/4661H05K 1/112H05K 2201/09472H05K 2201/0959H05K 1/114
84
PatentIndex Score
7
Cited by
51
References
37
Claims

Abstract

A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A board for mounting electronic circuit parts, comprising:
 a first connection terminal group including a plurality of connection terminals formed over a top surface of a substrate having through holes formed therein; 
 a second connection terminal group including a plurality of connection terminals formed at over a peripheral portion of a back surface of said substrate, said first connection terminal group being connected to said second connection terminal group by way of said through holes; and 
 a build-up multilayer interconnection layer formed on said top surface of said substrate and including at least one conductor layer and at least one insulator layer alternately stacked one on another, 
 said at least one insulator layer having a plurality of via holes for electric connection of said at least one conductor layer electrically connected to said through holes, 
 said first connection terminal group being densely formed on an outermost layer of said build-up multilayer interconnection layer, and said second connection terminal group being discretely formed at the peripheral portion of the back surface of said substrate. 
 
     
     
       2. The board according to  claim 1 , wherein said first connection terminal group is formed on said outermost layer of said build-up multilayer interconnection layer and those connection terminals in said first connection terminal group are electrically connected to said at least one conductor layer of said build-up multilayer interconnection layer by way of said via holes respectively. 
     
     
       3. The board according to  claim 1 , wherein said build-up multilayer interconnection layer is formed on said top surface and back surface of said substrate, each build-up multilayer interconnection layer including at least one conductor layer and at least one insulator layer alternately stacked one on another;
 said at least one insulator layer having a plurality of via holes for electric connection of said at least one conductor layer electrically connected to said through holes; 
 wherein said first connection terminal group and said second connection terminal group are respectively formed on outermost layers of said build-up multilayer interconnection layers; and 
 wherein those connection terminals located in a center portion of said first connection terminal group and said connection terminals of said second connection terminal group are electrically connected to said conductor layers of said build-up multilayer interconnection layers via associated via holes. 
 
     
     
       4. The board according to  claim 1 , wherein said build-up multilayer interconnection layer includes at least one conductor layer and at least one insulator layer alternately stacked one on another;
 wherein said at least one insulator layer has a plurality of via holes for connecting electrically the respective conductor layers; and 
 wherein said at least one conductor layer is laid out in forward and radial directions toward an outer peripheral portion of said board while being connected via associated via holes. 
 
     
     
       5. The board according to  claim 1 , wherein said insulator layer is formed using a photosensitive resin. 
     
     
       6. The board according to  claim 1 , wherein said at least one insulator layer contains an epoxy acrylate, a polyether sulfone, epoxy resin particles, and a photosensitive monomer. 
     
     
       7. The board according to  claim 1 , wherein said at least one insulator layer contains an epoxy acrylate, a polyether sulfone, melamine resin particles, and a photosensitive monomer. 
     
     
       8. The board according to  claim 1 , wherein said insulator layer is formed using a mixture of a resin obtained by photosensitizing a heat-curing resin, which is hardly soluble in acids or oxidizing agents, and heat-resistant resin particles soluble in acids or oxidizing agents. 
     
     
       9. The board according to  claim 8 , wherein said heat-resistant resin particles are at least one selected from the group including amino resin particles and epoxy resin particles. 
     
     
       10. The board according to  claim 8 , wherein said acids or oxidizing agents include chromic acid, chromates, permanganates, hydrochloric acid, phosphoric acid, formic acid, sulfuric acid and hydrofluoric acid. 
     
     
       11. A board for mounting electronic circuit parts, comprising:
 a first connection terminal group including a plurality of first connection terminals densely formed over a top surface of a substrate having through holes formed therein; 
 a second connection terminal group including a plurality of second connection terminals formed at at least a peripheral portion of a back surface of said substrate, said first connection terminal group being connected to said second connection terminal group by way of said through holes; and 
 a build-up multilayer interconnection layer formed on said top surface of said substrate and including at least one conductor layer and at least one insulator layer alternately stacked one on another, 
 said at least one insulator layer having a plurality of via holes for electrical connection of said at least one conductor layer electrically connected to said through holes, 
 said first connection terminal group being formed on an outermost layer of said build-up multilayer interconnection layer, and wherein said at least one insulator layer comprises a composite resin of a resin hardly soluble in acids or oxidizing agents, which is obtained by photosensitizing a heat-curing resin, and a thermoplastic resin, and heat-resistant resin particles soluble in acids or oxidizing agents. 
 
     
     
       12. The board according to  claim 11 , wherein said resin obtained by photosensitizing a heat-curing resin is at least one resin selected from the group including epoxy acrylates and photosensitive polyimides, and said thermoplastic resin is at least one resin selected from the group including polyether sulfones, polysulfones, phenoxy resins and polyethylenes. 
     
     
       13. A board for mounting electronic circuit parts, comprising a plurality of connection terminals and a plurality of signal lines formed on an insulator layer, said plurality of connection terminals being formed densely and being respectively connected to said signal lines, each of said signal lines comprising:
 a plurality of wiring patterns with different widths; and 
 a taper-shaped pattern connecting said wiring patterns with said different widths so as to have a width continuously changing, each of said signal lines having a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density, wherein side edges of said taper-shaped pattern are connected to associated side edges of said wiring patterns, and connected portions therebetween are rounded. 
 
     
     
       14. The board according to  claim 13 , wherein said width of said signal lines is set so as to become wider toward an outer peripheral portion of said board. 
     
     
       15. The board according to  claim 13 , wherein said insulator layer has a rough surface. 
     
     
       16. The board according to  claim 13 , wherein said insulator layer comprises heat-resistant resin particles hardly soluble in acids or oxidizing agents and cured heat resistant resin particles soluble in acids or oxidizing agents. 
     
     
       17. The board according to  claim 13 , wherein said wiring patterns with different widths include a first wiring pattern and a second wiring pattern wider than said first wiring pattern, wherein said taper-shaped pattern for connecting said first wiring pattern to said second wiring pattern has side edges inclined to a common center line of said first wiring pattern and said second wiring pattern by an angle of 10 to 45. 
     
     
       18. A board for mounting electronic circuit parts, comprising:
 a first connection terminal group including a plurality of connection terminals formed over a top surface of a substrate having through holes formed therein; 
 a second connection terminal group including a plurality of connection terminals formed at a peripheral portion of a back surface of said substrate, said first connection terminal group being connected to said second connection terminal group by way of said through holes; and 
 a build-up multilayer interconnection layer formed on said top surface of said substrate and including at least one conductor layer and at least one insulator layer alternately stacked one on another, said at least one insulator layer having a plurality of via holes for electric connection of said at least one conductor layer electrically connected to said through holes, wherein said at least one conductor layer is laid out in forward and radial directions toward the outer peripheral portion while being connected via associated via holes, 
 said first connection terminal group being densely formed on an outermost layer of said build-up multilayer interconnection layer, and said second connection terminal group being discretely formed at the peripheral portion of the back surface of said substrate, 
 said connection terminal in said first connection terminal group are electrically connected to said at least one conductor layer of said build-up multilayer interconnection layer by way of said via holes. 
 
     
     
       19. A board for mounting electronic circuit parts, comprising:
 a first connection terminal group including a plurality of connection terminals formed over a top surface of a substrate having through holes formed therein;   a second connection terminal group including a plurality of connection terminals formed over a peripheral portion of a back surface of said substrate, said first connection terminal group being connected to said second connection terminal group by way of said through holes; and   a build-up multilayer interconnection layer formed on said top surface of said substrate and including at least one conductor layer and at least one insulator layer alternately stacked one on another, the at least one conductor layer comprising an outer conductor pattern formed by a plurality of wiring lines,   said at least one insulator layer having a plurality of via holes for electric connection of said at least one conductor layer electrically connected to said through holes,   said first connection terminal group being densely formed on an outermost layer of said build-up multilayer interconnection layer,   said second connection terminal group being formed over the peripheral portion of the back surface of said substrate,   said first connection terminal group comprising internal pads and external pads positioned outside the internal pads, the internal pads including the via holes electrically connected to the through holes,   wherein the external pads are provided in a plurality of rows and include first external pads provided on an outermost row and second external pads provided in a row inside the outermost row, and   said first external pads and second external pads are each connected to the wiring lines extending towards the outer peripheral portion of the board.    
     
     
       20. The board according to claim 19, wherein said build-up multilayer interconnection layer is formed on said top surface and back surface of said substrate, each build-up multilayer interconnection layer including at least one conductor layer and at least one insulator layer alternately stacked one on another;
 said at least one insulator layer having a plurality of via holes for electric connection of said at least one conductor layer electrically connected to said through holes;   wherein said first connection terminal group and said second connection terminal group are respectively formed on outermost layers of said build-up multilayer interconnection layers; and   wherein those connection terminals located in a center portion of said first connection terminal group and said connection terminals of said second connection terminal group are electrically connected to said conductor layers of said build-up multilayer interconnection layers via associated via holes.    
     
     
       21. The board according to claim 19, wherein first to fifth rows of the first connection terminal group starting from the outermost row is used as external pads.  
     
     
       22. The board according to claim 19, wherein a solder resist is provided to protect the wiring lines.  
     
     
       23. The board according to claim 19, wherein said internal pads are electrically connected to an inner conductor layer extending towards the outer peripheral portion of the board.  
     
     
       24. The board according to claim 19, wherein said substrate is made of a glass-epoxy resin or a bismaleimidotriazine resin.  
     
     
       25. The board according to claim 19, wherein said insulating layer is made of resin.  
     
     
       26. The board according to claim 19, wherein said insulating layer has a roughened surface.  
     
     
       27. A board for mounting electronic circuit parts, comprising:
 a substrate having through holes formed therein and a first surface and a second surface, the second surface being positioned opposite to the first surface;   a first connection terminal group including a plurality of connection terminals formed at a predetermined area over the first surface of the substrate;   a second connection terminal group including a plurality of connection terminals formed over a peripheral portion of the second surface of the substrate; and   a build-up multilayer interconnection layer including conductor layers and insulator layers alternately stacked one on another on the first surface of the substrate, said conductor layers being electrically connected to each other by way of via holes and said conductor layers being electrically connected to said through holes;   wherein said first connection terminal group is formed on an outermost layer of said build-up multilayer interconnection layer, at least one connection terminal located at a central portion of the first connection terminal group is electrically connected to the conductor layers of the build-up multilayer interconnection layer by way of said via holes within said predetermined area, said first connection terminal group includes external pads located over an outer peripheral portion of the substrate, and said external pads are connected to the associated via holes by way of the conductor layer extending toward the outer peripheral portion of the board.    
     
     
       28. The board according to claim 27, wherein said substrate is a multilayer substrate.  
     
     
       29. The board according to claim 27, wherein said external pads include a plurality rows of pads.  
     
     
       30. The board according to claim 27, wherein one of the electronic circuit parts has a plurality of electrodes, wherein said first connection terminal group includes internal terminals located in the central portion of the first connection terminal group, wherein said internal terminals are constituted of the via holes located directly below the corresponding electrodes.  
     
     
       31. The board according to claim 27, wherein one of the electronic circuit parts has a plurality of electrodes, wherein said first connection terminal group includes internal terminals located in the central portion of the first connection terminal group, wherein said internal terminals include a combination of pads and the via holes.  
     
     
       32. The board according to claim 31, wherein said internal terminals include the pads and the via holes that are located directly below the electrodes of one of the electronic circuit parts.  
     
     
       33. The board according to claim 32, wherein said pads are connected to said via holes by way of the conductor layers.  
     
     
       34. The board according to claim 27, wherein each of said via holes has a diameter of about 80 μm or less.  
     
     
       35. The board according to claim 27, wherein the second connection terminal group has a surface exposed outwardly.  
     
     
       36. The board according to claim 35, wherein the exposed surface of the connection terminal group is covered with a gold layer.  
     
     
       37. The board according to claim 27, wherein the first connection terminal group includes internal terminals located in the central portion of the first connection terminal group, and the internal terminals include pads and via holes connected to the pads through conductor patterns formed over the first surface of the substrate, respectively.

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