Semiconductor device having a vertically-oriented conductive region that electrically connects a transistor structure to a substrate

Abstract

In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

We claim: 
     
       1. A semiconductor device comprising:
 a body of semiconductor material; and   a charge compensation region including a trench formed in the body of semiconductor material, wherein the trench comprises a pair of opposite conductivity type single crystal semiconductor layers overlying surfaces of the trench, and wherein a first intrinsic layer separates the pair, and wherein a passivation liner is formed overlying an outermost one of the pair.   
     
     
       2. The device of  claim 1 , wherein the passivation liner comprises an oxide. 
     
     
       3. The device of  claim 1  further comprising a conductive layer coupled to the charge compensation region. 
     
     
       4. The device of  claim 1 , wherein the passivation liner comprises a dielectric material. 
     
     
       5. The device of  claim 1 , wherein the passivation liner comprises a nitride. 
     
     
       6. The device of  claim 1 , wherein the passivation liner comprises an oxide and a nitride. 
     
     
       7. The device of  claim 1 , wherein the charge compensation region further includes a void. 
     
     
       8. The device of  claim 7 , wherein the void is formed at a centralized portion of the charge compensation region. 
     
     
       9. A semiconductor device comprising:
 a body of semiconductor material; and   a trench formed in the body of semiconductor material;   a first layer comprising a single crystal semiconductor material formed overlying surfaces of the trench, wherein the first layer comprises a first conductivity type;   a first intrinsic layer formed overlying the first layer;   a second layer comprising a single crystal semiconductor material formed overlying the first intrinsic layer, wherein the second layer comprises a second conductivity type, and wherein the first intrinsic layer is configured to reduce intermixing of dopants between the first and second layers; and   a passivation layer formed overlying the second layer to form a charge compensation region.   
     
     
       10. The device of  claim 9  further comprising a conductive layer coupled to the charge compensation region. 
     
     
       11. The device of  claim 9 , wherein the trench includes a void. 
     
     
       12. The device of  claim 9 , wherein the passivation layer comprises a dry oxide layer. 
     
     
       13. A semiconductor device comprising:
 a body of semiconductor material having first and second opposing major surfaces;   a trench formed in the body of semiconductor material;   a first semiconductor layer of a first conductivity type formed adjoining surfaces of the trench;   a first intrinsic layer formed adjoining the first semiconductor layer;   a second semiconductor layer of a second conductivity type formed adjacent to the first intrinsic to form a charge compensated region;   a passivation layer formed overlying the second semiconductor layer;   a first doped region in the body of semiconductor material formed adjacent the charge compensated region, wherein the first doped region comprises the second conductivity type;   a second doped region formed in the first doped region and comprising the first conductivity type; and   a control electrode formed adjacent the first and second doped regions.   
     
     
       14. The device of  claim 13  further comprising a conductive layer coupled to the charge compensated region. 
     
     
       15. The device of  claim 13 , wherein the control electrode comprises a spacer gate structure. 
     
     
       16. The device of  claim 13 , wherein the passivation layer comprises an oxide layer. 
     
     
       17. The device of  claim 13 , wherein the passivation layer comprises a nitride layer. 
     
     
       18. The device of  claim 13 , wherein the passivation layer comprises an oxide layer and a nitride layer. 
     
     
       19. The device of  claim 13 , wherein the charge compensated region has a void. 
     
     
       20. A semiconductor device comprising:
 a substrate;   a semiconductor layer overlying the substrate, wherein the semiconductor layer has a major surface spaced apart from the substrate;   a vertically-oriented conductive region adjacent to the major surface and extending towards the substrate;   a horizontally-oriented doped region of a first conductivity type adjacent to the major surface;   a body region of a second conductivity type adjacent to another portion of the major surface, wherein the horizontally-oriented doped region adjoins the body region;   a first conductive layer configured to reduce gate to drain capacitance; and   a gate electrode spaced apart from and electrically insulated from the body region and the horizontally-oriented doped region,   wherein:
 a transistor structure of the semiconductor device comprises the horizontally-oriented doped region, the body region, and the gate electrode; 
 the first conductive layer is electrically connected to the transistor structure; and 
 the vertically-oriented conductive region electrically connects the transistor structure and the substrate to each other.  
   
     
     
       21. The device of claim 20, wherein the vertically-oriented conductive region comprises a second conductive layer.  
     
     
       22. The device of claim 20, wherein the horizontally-oriented doped region is at least part of a drain region of the transistor structure.  
     
     
       23. The device of claim 22, wherein the transistor structure further comprises a source region of the first conductivity type adjoining the body region, wherein the source region is electrically connected to the first conductive layer.  
     
     
       24. The device of claim 20, further comprising a doped region of the second conductivity type below the horizontally-oriented doped region and within the semiconductor layer, wherein the doped region has a higher dopant concentration as compared to the semiconductor layer.  
     
     
       25. A semiconductor device comprising:
 a substrate;   a semiconductor layer overlying the substrate, having a major surface spaced apart from the substrate, and defining a trench adjacent to the major surface and extending towards the substrate;   a transistor structure comprising:
 a first current-carrying electrode of a first conductivity type adjacent to the major surface; 
 at least a portion of a body region of a second conductivity type adjacent to the major surface; and 
 a control electrode overlying the major surface; 
   a doped region of the second conductivity type having a higher dopant concentration as compared to the semiconductor layer, wherein the doped region underlies and adjoins the first current-carrying electrode of the transistor structure; and   a first conductive layer adjacent to the major surface and extending into the trench, wherein the first conductive layer is configured to provide a vertical current path between the transistor structure and the substrate.    
     
     
       26. The device of claim 25, further comprising a body contact region, wherein another portion of the body region underlies the body contact region.  
     
     
       27. The device of claim 25, wherein the doped region adjoins the first conductive layer.  
     
     
       28. The device of claim 25, wherein the doped region adjoins the body region.  
     
     
       29. The device of claim 25, wherein the first current-carrying electrode comprises a drain region of the transistor structure.  
     
     
       30. The device of claim 25, wherein the doped region is spaced apart from the semiconductor substrate.  
     
     
       31. The device of claim 25, wherein the at least a portion of the body region comprises a channel region of the transistor structure.  
     
     
       32. The device of claim 31, wherein the transistor structure is a lateral transistor.  
     
     
       33. The device of claim 31, wherein the transistor structure further comprises a source region, wherein:
 the source region has the first conductivity type and is adjacent to the major surface; and   a drain region of the transistor structure comprises the first current-carrying electrode.    
     
     
       34. The device of claim 25, further comprising a conductive electrode, wherein the control electrode is a gate electrode of the transistor structure, and the conductive electrode is configured to reduce gate to drain capacitance.  
     
     
       35. The device of claim 34, wherein the conductive electrode includes a first portion extending into the trench and a second portion overlying the major surface.  
     
     
       36. The device of claim 34, wherein the transistor structure further comprises a source region in the body region, wherein the source region is electrically coupled to the conductive electrode.  
     
     
       37. A semiconductor device comprising:
 a substrate;   a semiconductor layer overlying the substrate, having a major surface spaced apart from the substrate, and having an as-formed dopant concentration, wherein a portion of the semiconductor layer lies at a sidewall that defines at least part of a trench, and the portion has the as-formed dopant concentration;   a transistor structure comprising:
 a first current-carrying electrode of a first conductivity type adjacent to the major surface; 
 at least a portion of a body region of a second conductivity type adjacent to the major surface; and 
 a control electrode overlying the major surface; and 
   a first conductive layer adjacent to the major surface and extending into the trench, wherein the first conductive layer is configured to provide a vertical current path between the transistor and the substrate.    
     
     
       38. A semiconductor device comprising:
 a substrate;   a semiconductor layer overlying the substrate and having a major surface spaced apart from the substrate;   a transistor structure comprising:
 a first current-carrying electrode of a first conductivity type adjacent to the major surface; 
 at least a portion of a body region of a second conductivity type adjacent to the major surface; and 
 a control electrode overlying the major surface; 
   a first conductive layer adjacent to the major surface and extending vertically towards the substrate, wherein the first conductive layer is configured to provide a vertical current path between the transistor structure and the substrate; and   a second conductive layer overlies the major surface, wherein the second conductive layer is configured to reduce gate to drain capacitance and to be at substantially a same voltage as the first current-carrying electrode of the transistor structure.    
     
     
       39. The device of claim 38, wherein:
 the semiconductor layer has an as-formed dopant concentration;   a portion of the semiconductor layer lies at a sidewall that defines at least a portion of a trench adjacent to the major surface and extending towards the substrate; and   the portion has the as-formed dopant concentration.