Power semiconductor having a lightly doped drift and buffer layer

Abstract

A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.

What is claimed is: 
     
       1. A power MOS transistor of the a planar type, comprising:
 a semiconductor body having a first and a second surface, 
 body regions of a first conductivity type and a first dopant concentration formed in the first surface; 
 a highly doped source region of a second conductivity type having a first dopant concentration, provided at the first surface; 
 a contact arrangement provided at the first surface, the contact arrangement comprising a gate electrode over an insulating layer on the first surface and a source electrode, directly over the first surface and in contact with the source region; 
 at least two deep, lightly doped well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween; 
 a highly doped drain contact layer of the second conductivity type and a second dopant concentration provided in or on the second surface of the semiconductor body; and 
 an electrode provided on the a free surface of the drain contact layer;, 
 wherein underneath and between the deep well regions of the first conductivity type a lightly doped drift and buffer layer of the second conductivity type and a third dopant concentration is provided, wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and the a bottom of the a deepest well region of the deep well regions and which is at least equal to the minimum lateral distance between the deep well regions, 
 wherein the minimum vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the deep well regions;, and 
 wherein the minimum vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount. 
 
     
     
       2. The power MOS transistor of  claim 1 , wherein the second third dopant concentration in the drift and buffer layer increases towards the drain contact layer. 
     
     
       3. The power MOS transistor of  claim 1 , wherein the power MOS transistor is of the a superjunction type, wherein the deep, lightly doped well regions are constituted by a basically substantially vertical stack of separated, bubble-shaped well regions. 
     
     
       4. The power MOS transistor of  claim 1 , wherein the semiconductor body and the drift and buffer layer comprise a semiconductor substrate and the drain contact layer comprises an ion implantation layer within the semiconductor substrate. 
     
     
       5. The power MOS transistor of  claim 1 , wherein the second third dopant concentration is constant through the drift and buffer layer. 
     
     
       6. The power MOS transistor of  claim 1 , wherein an interface between the drift and buffer layer and the drain contact layer comprises valleys under the deep well regions. 
     
     
       7. A power semiconductor, comprising:
 a semiconductor body having a first and a second surface, body regions of a first conductivity type and a first dopant concentration formed in the first surface;   a highly doped source region of a second conductivity type provided at the first surface;   a contact arrangement provided at the first surface;   at least two deep, lightly doped well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween;   a highly doped drain contact layer of the second conductivity type provided in or on the second surface of the semiconductor body; and   an electrode provided on a free surface of the drain contact layer,   wherein underneath and between the deep well regions of the first conductivity type a lightly doped drift and buffer layer of the second conductivity type and a third dopant concentration is provided,   wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and a bottom of a deepest well region of the deep well regions and which is at least equal to the minimum lateral distance between the deep well regions,   wherein the minimum vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the deep well regions, and   wherein the minimum vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.   
     
     
       8. The power semiconductor of claim 7, wherein the contact arrangement comprises a gate electrode over an insulating layer on the first surface and a source electrode, over the first surface and in contact with the source region. 
     
     
       9. The power semiconductor of claim 7, wherein the contact arrangement comprises a gate electrode provided within a trench which extends into the first surface. 
     
     
       10. The power semiconductor of claim 7, wherein the power semiconductor is a planar type power MOS transistor. 
     
     
       11. The power semiconductor of claim 7, wherein power semiconductor is a trench type power MOS transistor. 
     
     
       12. The power semiconductor of claim 7, wherein the contact arrangement is provided on the first surface. 
     
     
       13. The power semiconductor of claim 7, wherein the contact arrangement is provided in the first surface. 
     
     
       14. The power semiconductor of claim 7, wherein the power semiconductor is capable of blocking at least one reverse voltage within a range of 40 V to 1200V. 
     
     
       15. The power semiconductor of claim 7, wherein the third dopant concentration in the drift and buffer layer is substantially constant throughout the drift and buffer layer. 
     
     
       16. The power semiconductor of claim 7, wherein the third dopant concentration in the drift and buffer layer increases from the deep well regions towards the drain contact layer. 
     
     
       17. The power semiconductor of claim 7, wherein the vertical extension of the drift and buffer layer is determined such that the total amount of the dopants per unit area is within a range of a factor of 1.5-2.5 of a charge at breakdown voltage. 
     
     
       18. The power semiconductor of claim 7, wherein the drift and buffer layer further comprises a fourth dopant concentration which is located between the deep well regions,
 wherein the third dopant concentration is located underneath the deep well regions and is within a range of a factor of 0.01 to 3 of the fourth dopant concentration.   
     
     
       19. The power semiconductor of claim 7, wherein the drift and buffer layer further comprises a fourth dopant concentration which is located underneath the deep well regions,
 wherein the fourth dopant concentration is within a range of a factor of 0.01 to 3 of the third dopant concentration which is located between the deep well regions.   
     
     
       20. A power MOS transistor of a trench type, comprising:
 a semiconductor body having a first and a second surface, body regions of a first conductivity type and a first dopant concentration formed in the first surface;   a highly doped source region of a second conductivity type provided at the first surface;   a contact arrangement which extends into the first surface;   at least two deep, lightly doped well regions of the first conductivity type having a second dopant concentration, and having a minimum lateral distance therebetween;   a highly doped drain contact layer of the second conductivity type provided in or on the second surface of the semiconductor body; and   an electrode provided on a free surface of the drain contact layer,   wherein underneath and between the deep well regions of the first conductivity type a lightly doped drift and buffer layer of the second conductivity type and a third dopant concentration is provided,   wherein the drift and buffer layer has a minimum vertical extension between the drain contact layer and a bottom of a deepest well region of the deep well regions and which is at least equal to the minimum lateral distance between the deep well regions,   wherein the minimum vertical extension of the drift and buffer layer amounts to at least twice the minimum lateral distance between the deep well regions, and   wherein the minimum vertical extension of the drift and buffer layer between the drain contact layer and the bottom of the deepest well region is determined such that a total amount of its dopants per unit area is larger than a breakdown charge amount.