Dual high-K oxides with SiGe channel

Abstract

A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices ( 50, 52 ) and core transistor devices ( 51, 53 ) on a single substrate ( 15 ) having a silicon germanium channel layer ( 21 ) in the PMOS device areas ( 112, 113 ), where each DGO transistor device ( 50, 52 ) includes a metal gate ( 25 ), an upper gate oxide region ( 60, 84 ) formed from a second, relatively higher high-k metal oxide layer ( 24 ), and a lower gate oxide region ( 58, 84 ) formed from a first relatively lower high-k layer ( 22 ), and where each core transistor device ( 51, 53 ) includes a metal gate ( 25 ) and a core gate dielectric layer ( 72, 98 ) formed from only the second, relatively higher high-k metal oxide layer ( 24 ).

What is claimed is: 
     
       1. A semiconductor fabrication process comprising:
 providing a wafer comprising a first semiconductor layer having a first PMOS device area, a second PMOS device area, and an NMOS device area; 
 forming a compressive silicon germanium layer on at least the first PMOS device area, and the second PMOS device area; 
 selectively forming a deposited first high-k dielectric layer over the compressive silicon germanium layer of the first PMOS device area, where the first high-k dielectric layer is formed from a first dielectric material which has a first dielectric constant value of 7.0 or greater; 
 depositing a second high-k dielectric layer over the first high-k dielectric layer in the first PMOS device area, over the compressive silicon germanium layer in the second PMOS device area, and over the first semiconductor layer in the NMOS device area, where the second high-k dielectric layer is formed from a second dielectric material which has a dielectric constant value that is higher than the first dielectric constant value; and 
 depositing one or more gate electrode layers over the second high-k dielectric layer 
 wherein a first device formed in the first PMOS device area is characterized as a PMOS transistor that includes a portion of the deposited first high-k dielectric layer and a portion of the second high-k dielectric layer and a second device formed in the second PMOS device area is characterized as a PMOS transistor that includes a portion of the second high-k dielectric layer and does not include a portion of the deposited first high-k dielectric layer. 
 
     
     
       2. The semiconductor fabrication process of  claim 1 , where providing the wafer comprises providing a first semiconductor layer as a semiconductor-on-insulator (SOI) substrate structure or bulk substrate structure. 
     
     
       3. The semiconductor fabrication process of  claim 1 , where forming the compressive silicon germanium layer comprises epitaxially growing silicon germanium to a predetermined thickness. 
     
     
       4. The semiconductor fabrication process of  claim 1 , where selectively forming the deposited first high-k dielectric layer comprises depositing a silicate or metal oxy-nitride material. 
     
     
       5. The semiconductor fabrication process of  claim 1 , where selectively forming the deposited first high-k dielectric layer comprises depositing a layer of Hf x Si 1-x O y  or Hf x Si 1-x O y N z  over at least the compressive silicon germanium layer. 
     
     
       6. The semiconductor fabrication process of  claim 1 , where selectively forming the deposited first high-k dielectric layer comprises depositing a silicate or metal oxy-nitride material in a deposition process which occurs at a temperature that is selected to reduce or eliminate germanium diffusion from the compressive silicon germanium layer. 
     
     
       7. The semiconductor fabrication process of  claim 1 , where selectively forming the deposited first high-k dielectric layer comprises:
 blanket depositing the first high-k dielectric layer over the first PMOS device area, the second PMOS device area, and the NMOS device area; 
 forming a patterned etch mask to cover the compressive silicon germanium layer in the first PMOS device area; and 
 selectively etching the first high-k dielectric layer to expose the NMOS device area and the second PMOS device area while leaving the first high-k dielectric layer over the compressive silicon germanium layer in the first PMOS device area. 
 
     
     
       8. The semiconductor fabrication process of  claim 1 , where depositing the second high-k dielectric layer comprises depositing a layer of HfO 2  over the first high-k dielectric layer in the first PMOS device area and over the first semiconductor layer in the NMOS device area, and over the compressive silicon germanium layer in the second PMOS device layer. 
     
     
       9. A method of forming devices comprising:
 forming a first gate dielectric device in a first region of a semiconductor substrate, wherein the first gate dielectric device comprises a first gate dielectric formed by depositing a first high-k dielectric layer and a second high-k dielectric layer over a first channel region of the semiconductor substrate, where the first high-k dielectric layer has a first dielectric constant value that is smaller than a second dielectric constant value for the second high-k dielectric layer; and 
 forming a second gate dielectric device in a second region of the semiconductor substrate, wherein the second gate dielectric device comprises a second gate dielectric that is thinner than the first gate dielectric and that is formed by depositing the second high-k dielectric layer over a second channel region of the semiconductor substrate; 
 wherein the first channel region and the second channel region are characterized as channel regions for first conductivity type devices; 
 wherein the first conductivity type devices are characterized as PMOS devices. 
 
     
     
       10. The method of  claim 9 , where forming the first gate dielectric device and the second gate dielectric device further comprises depositing a gate electrode material over the second high-k dielectric layer. 
     
     
       11. The method of  claim 9 , further comprising epitaxially growing a compressive silicon germanium layer on the first channel region of the semiconductor substrate prior to depositing the first high-k dielectric layer. 
     
     
       12. The method of  claim 11 , where forming the first gate dielectric device comprises:
 depositing a first high-k dielectric layer of Hf x Si 1-x O y  or Hf x Si 1-x O y N z  over the compressive silicon germanium layer; and 
 depositing a second high-k dielectric layer of HfO 2  over the first high-k dielectric layer. 
 
     
     
       13. The method of  claim 12 , where forming the second gate dielectric device comprises depositing the second high-k dielectric layer of HfO 2  over the second channel region. 
     
     
       14. The method of  claim 11 , where forming the first gate dielectric device comprises depositing the first high-k dielectric layer as a silicate or metal oxy-nitride material in a deposition process which occurs at a temperature that is selected to reduce or eliminate germanium diffusion from the compressive silicon germanium layer. 
     
     
       15. The method of  claim 9 , further comprising epitaxially growing a silicon carbide layer on the first channel region of the semiconductor substrate prior to depositing the first high-k dielectric layer. 
     
     
       16. The method of  claim 9 , further comprising:
 forming a third gate dielectric device in a third region of the semiconductor substrate, wherein the third gate dielectric device comprises a third gate dielectric formed by depositing the first high-k dielectric layer and the second high-k dielectric layer over a third channel region of the semiconductor substrate; and 
 forming a fourth gate dielectric device in a fourth region of the semiconductor substrate, wherein the fourth gate dielectric device comprises a fourth gate dielectric that is thinner than the third gate dielectric and that is formed by depositing the second high-k dielectric layer over a fourth channel region of the semiconductor substrate; 
 wherein the third channel region and the fourth channel region are characterized as channel regions for second conductivity type devices, the second conductivity type devices are of a conductivity type that is opposite to a conductivity type of the first conductivity type devices. 
 
     
     
       17. A method for forming a semiconductor device comprising:
 providing a semiconductor substrate comprising first and second device areas, wherein the first device area and the second device area are each characterized as a first conductivity type device area; 
 selectively forming a first deposited high-k dielectric layer over the first device area, where the first high-k dielectric layer has a first dielectric constant value of 7.0 or greater; 
 forming a second deposited high-k dielectric layer over the first high-k dielectric layer in the first device area and over the semiconductor substrate in the second device area, where the second high-k dielectric layer has a dielectric constant value that is higher than the first dielectric constant value; 
 forming one or more gate electrode layers over the second high-k dielectric layer; and 
 selectively etching the one or more gate electrode layers to form one or more gate electrode structures over the first and second device areas; 
 wherein a first device formed in the first device area is characterized as a PMOS transistor that includes a portion of the first deposited high-k dielectric layer and a portion of the second deposited high-k dielectric layer and a second device formed in the second device area is characterized as a PMOS transistor that includes a portion of the second deposited high-k dielectric layer and does not include a portion of the first deposited high-k dielectric layer; 
 wherein the first device area and the second device area are each characterized as a PMOS device area. 
 
     
     
       18. The method of  claim 17 , further comprising epitaxially growing a compressive silicon germanium layer on one or more PMOS channel regions of the semiconductor substrate in the first and second device areas prior to forming the first deposited high-k dielectric layer. 
     
     
       19. The method of  claim 18 , where selectively forming the first deposited high-k dielectric layer comprises depositing a layer of Hf x Si 1-x O y  or Hf x Si 1-x O y N z  over at least the compressive silicon germanium layer in a deposition process which occurs at a temperature that is selected to reduce or eliminate germanium diffusion from the compressive silicon germanium layer. 
     
     
       20. The method of  claim 17 , where selectively forming the first deposited high-k dielectric layer comprises:
 depositing the first deposited high-k dielectric layer as a layer of silicate or metal oxy-nitride over the first and second device areas; and 
 selectively etching the first deposited high-k dielectric layer from the second device area to expose the semiconductor substrate in the second device area. 
 
     
     
       21. The method of  claim 17 , where forming the second high-k dielectric layer comprises depositing a layer of HfO 2  over the first high-k dielectric layer in the first device area and over the semiconductor substrate in the second device area. 
     
     
       22. The method of  claim 17 , where selectively forming the first deposited high-k dielectric layer over the first device area reduces a thickness measure for the first deposited high-k dielectric layer in the first device area that is required to meet a predetermined electrical oxide thickness (Tox) requirement as compared to forming the first deposited high-k dielectric layer with a material having a higher dielectric constant value. 
     
     
       23. A semiconductor fabrication process comprising:
 selectively forming a first high-k dielectric layer in a PMOS region of a semiconductor substrate, where the first high-k dielectric layer is formed from a first dielectric material which has a first high-k dielectric constant value; and   forming a second high-k dielectric layer over the first high-k dielectric layer in the PMOS region and over an NMOS region of the semiconductor substrate, where the second high-k dielectric layer is formed from a second dielectric material which has a high-k dielectric constant value that is higher than the first high-k dielectric constant value.   
     
     
       24. The semiconductor fabrication process of  claim 23 , further comprising depositing one or more gate electrode layers over the second high-k dielectric layer. 
     
     
       25. The semiconductor fabrication process of  claim 24 , further comprising selectively etching the one or more gate electrode layers to form one or more gate electrode structures over the PMOS and NMOS regions.