USRE46271EExpiredUtilityPatentIndex 52

Semiconductor device

Assignee: TOSHIBA KKPriority: Feb 14, 2005Filed: Nov 5, 2014Granted: Jan 10, 2017

Est. expiryFeb 14, 2025(expired)· nominal 20-yr term from priority

Inventors:ICHIHARA REIKA TSUCHIYA YOSHINORI KOYAMA MASATO NISHIYAMA AKIRA

H10D 84/0144H10D 64/691H10D 64/681H10D 64/68H10D 84/0181H10D 84/038H01L 21/823462H01L 21/823857

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Claims

Abstract

A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Claims

exact text as granted — not AI-modified

The invention claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming an n-type semiconductor region and a p-type semiconductor region on a semiconductor substrate;
forming a first gate dielectric layer above the n-type semiconductor region;
forming a second gate dielectric layer above the p-type semiconductor region, the second gate dielectric layer having a composition different from that of the first gate dielectric layer; and
forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer,
such that a portion of the first gate dielectric layer in contact with the gate electrode layer and a portion of the second gate dielectric layer in contact with the gate electrode layer include oxygen, a first element of at least one element selected from the group consisting of Zr, Hf, Ti, Ta, Nb, V, Sc, Y, a lanthanoide series and a actinide series, and
said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region includes making the atomic density of the first element in the portion of the second gate dielectric layer be lower than the atomic density of the first element in the portion of the first gate dielectric layer.

2. The method according to claim 1 , wherein said forming a second gate dielectric layer includes forming the second gate dielectric layer with a second element including one selected from the group consisting of Al, Si and Ge.

3. The method according to claim 1 , further comprising:
removing the first gate dielectric layer on the p-type semiconductor region, after said forming a first gate dielectric layer and before said forming a second gate dielectric layer.

4. The method according to claim 3 , further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.

5. The method according to claim 4 , further comprising:
forming an insulating layer over the p-type semiconductor region and the n-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and
flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.

6. The method according to claim 1 , wherein said forming a second gate dielectric layer above the p-type semiconductor region includes forming the second gate dielectric layer above the p-type semiconductor region with the first gate dielectric layer interposed therebetween.

7. The method according to claim 6 , further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.

8. The method according to claim 7 , further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and
flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.

9. The method according to claim 6 , wherein said forming a second gate dielectric layer above the p-type semiconductor region includes forming the second gate dielectric layer so as to have a thickness of one or more mono layers and 2 nm or less.

10. The method according to claim 1 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χB−χA)×(d A +d B )≧3.9

is satisfied by electronegativity (χA) and an atomic radius (d A , a unit thereof is Å) of a metal element constituting the gate electrode layer and by electronegativity (χB) and an atomic radius (d B ) of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the first gate dielectric layer facing the gate electrode layer.

11. The method according to claim 10 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χC−χA)×(d A +d C )≦0.7

is satisfied, wherein χC and d C (a unit thereof is Å) are electronegativity and an atomic radius of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the second gate dielectric layer above the p-type semiconductor region facing the gate electrode layer.

12. The method according to claim 1 , wherein said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, includes making the atomic density of the first element contained in the second gate dielectric layer be 50% or less of atomic density of the first element contained in the first gate dielectric layer.

13. The method according to claim 1 , wherein said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, includes making a portion of the first gate electrode layer in contact with the first gate dielectric layer and a portion of the second gate electrode layer in contact with the second gate dielectric layer include the same metal element.

14. The method according to claim 1 , wherein said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, includes making a portion of the first gate electrode layer in contact with the first gate dielectric layer and a portion of the second gate electrode layer in contact with the second pate gate dielectric layer include at least one metal element selected from the group consisting of Ta, La, Er, Zr, Hf, Ti and La.

15. A method of manufacturing a semiconductor device, comprising:
forming an n-type semiconductor region and a p-type semiconductor region on a semiconductor substrate;
forming a second gate dielectric layer above the n-type semiconductor region and the p-type semiconductor region;
forming a first gate dielectric layer above the n-type semiconductor region, the first gate dielectric layer being made of an insulating material different from that of the second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer being formed of an oxide layer including a first element of at least one metal element selected from the group consisting of Zr, Hf, Ti, Ta, Nb, V, Sc, Y, a lanthanoide series and a actinide series; and
forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, wherein an atomic density of the first element in a portion of the second pate gate dielectric layer in contact with the gate electrode layer is lower than an atomic density of the first element in a portion of the first pate gate dielectric layer in contact with the gate electrode layer.

16. The method according to claim 15 , wherein said forming a second gate dielectric layer includes forming the second gate dielectric layer with a material including one selected from the group consisting of Al, Si and Ge.

17. The method according to claim 15 , wherein said forming a first gate dielectric layer above the n-type semiconductor region includes forming the first gate dielectric layer above the n-type semiconductor region with the second gate dielectric layer interposed therebetween.

18. The method according to claim 17 , further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.

19. The method according to claim 18 , further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and
flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.

20. The method according to claim 17 , wherein said forming a first gate dielectric layer above the n-type semiconductor region includes forming the first gate dielectric layer so as to have a thickness of one or more mono layers and 2 nm or less.

21. The method according to claim 15 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χB−χA)×(d A +d B )≧3.9

22. The method according to claim 21 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χC−χA)×(d A +d C )≦0.7

23. A semiconductor device comprising:
a semiconductor substrate; an nMISFET including a first dielectric disposed above the semiconductor substrate and a first metal gate electrode formed on the first dielectric; and a pMISFET including a second dielectric disposed above the semiconductor substrate and a second metal gate electrode disposed above the second dielectric, wherein the first dielectric in contact with the first metal gate electrode and the second dielectric in contact with the second metal gate electrode include a first element of at least one element selected from the group consisting of Zr, Hf, Ti, Ta, Nb, V, Sc, Y, a lanthanoide series and an actinide series, and at least the first dielectric includes a second element selected from a group consisting of Al, Si and Ge, and an atomic density of the second element in the second dielectric is lower than an atomic density of the second element in the first dielectric.

24. The semiconductor device according to claim 23, wherein the second dielectric comprises a hafnium (Hf) oxide layer contacting the second metal gate electrode.

25. The semiconductor device according to claim 24, wherein the hafnium oxide layer has a thickness of 2 nm or less.

26. The semiconductor device according to claim 25, wherein the second dielectric further comprises a silicon oxide (SiO 2 ) layer between the semiconductor substrate and the hafnium oxide layer.

27. The semiconductor device according to claim 23, wherein the second element is aluminum (Al).

28. The semiconductor device according to claim 23, wherein the first element is titanium (Ti).

29. The semiconductor device according to claim 23, wherein the first element is tantalum (Ta).

30. The semiconductor device according to claim 23, further comprising a tungsten (W) metal layer formed on each of the first and second metal gate electrodes.

31. The semiconductor device according to claim 30, wherein the first and second metal gate electrodes include titanium (Ti).

32. The semiconductor device according to claim 23, wherein the first and second metal gate electrodes include titanium (Ti).

33. The semiconductor device according to claim 23, wherein the second element is silicon (Si).

34. A method of manufacturing a semiconductor device, comprising:
forming an nMISFET including a first dielectric disposed above a semiconductor substrate and a first metal gate electrode formed on the first dielectric; and forming a pMISFET including a second dielectric disposed above the semiconductor substrate and a second metal gate electrode disposed above the second dielectric, wherein the first dielectric in contact with the first metal gate electrode and the second dielectric in contact with the second metal gate electrode include a first element of at least one element selected from the group consisting of Zr, Hf, Ti, Ta, Nb, V, Sc, Y, a lanthanoide series and an actinide series, and at least the first dielectric includes a second element selected from a group consisting of Al, Si and Ge, and an atomic density of the second element in the second dielectric is lower than an atomic density of the second element in the first dielectric.

35. The method according to claim 34, wherein the second dielectric comprises a hafnium (Hf) oxide layer contacting the second metal gate electrode.

36. The method according to claim 35, wherein the hafnium oxide layer has a thickness of 2 nm or less.

37. The method according to claim 34, wherein the hafnium oxide layer is formed by atomic layer deposition.

38. The method according to claim 36, wherein the second dielectric further comprises a silicon oxide (SiO 2 ) layer between the semiconductor substrate and the hafnium oxide layer.

39. The method according to claim 38, wherein the hafnium oxide layer is formed by atomic layer deposition.

40. The method according to claim 34, wherein the selected second element is aluminum (Al).

41. The method according to claim 34, wherein the first element is titanium (Ti).

42. The method according to claim 34, wherein the first element is tantalum (Ta).

43. The method according to claim 34, further comprising a tungsten (W) metal layer formed on each of the first and second metal gate electrodes.

44. The method according to claim 43, wherein the first and second metal gate electrodes includes titanium (Ti).

45. The method according to claim 34, wherein the first and second metal gate electrodes includes titanium (Ti).

46. The method according to claim 34, wherein the second element is silicon (Si).

47. The method according to claim 34, wherein the first and second metal gate electrodes are formed by a damascene processing method.

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