Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby

Abstract

In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

What is claimed is: 
     
       1. A method of programming a nonvolatile memory device including strings extending from intersections of first through nth bit lines (n being an integer of 1 or more) and a plurality of string selection lines, each string including memory cells formed in a direction perpendicular to a substrate to have multiple layers of memory cells, wherein the perpendicular direction is a Y-direction, the string selection lines extend in a Z-direction and the bit lines extend in an X-direction, comprising:
 programming a first group of memory cells, corresponding to a part of the plurality of string selection lines, from among the memory cells at the multiple layers; and 
 after the first group of the memory cells is all programmed, programming a second group of memory cells, corresponding to remaining string selection lines, from among the memory cells at the multiple layers, 
 wherein each of the programming a first group of memory cells and the programming a second group of memory cells comprises programming memory cells at each layer of an YZ plane with multi-bit data according to a shadow programming method, and 
 wherein, where memory cells at an Nth layer (N being an integer of 1 or more) of the YZ plane are programmed, remaining memory cells at an XZ plane corresponding to the Nth layer are programmed before memory cells at another layer of the YZ plane are programmed. 
 
     
     
       2. The program method of  claim 1 , wherein the part of the plurality of string selection lines comprises at least first, second, and third string selection lines, and wherein
 the programming a first group of memory cells comprises 
 sequentially performing a first programming operation on first memory cells at a first layer of the YZ plane and defined by the first string selection line and the first through nth bit lines, a second programming operation on second memory cells, defined by the second string selection line and the first through nth bit lines, from among remaining memory cells located at an XZ plane corresponding to the first layer of the YZ plane, and a third programming operation on third memory cells, defined by the third string selection line and the first through nth bit lines, from among the remaining memory cells located at the XZ plane corresponding to the first layer of the YZ plane, and 
 after the first through third programming operations, programming memory cells at a second layer of the YZ plane and in the first group. 
 
     
     
       3. The program method of  claim 2 , wherein the remaining string selection lines comprise at least fourth, fifth, and sixth string selection lines, and wherein
 the programming a second group of memory cells comprises 
 sequentially performing a fourth programming operation on fourth memory cells at a first layer of the YZ plane and defined by the fourth string selection line and the first through nth bit lines, a fifth programming operation on second memory cells, defined by the fifth string selection line and the first through nth bit lines, from among remaining memory cells located at an XZ plane corresponding to the first layer of the YZ plane, and a sixth programming operation on third memory cells, defined by the sixth string selection line and the first through nth bit lines, from among the remaining memory cells located at the XZ plane corresponding to the first layer of the YZ plane, and 
 after the fourth through sixth programming operations, programming memory cells at a second layer of the YZ plane and in the second group. 
 
     
     
       4. The program method of  claim 3 , wherein the bit lines are arranged to be vertical to the YZ plane, and the bit lines are activated simultaneously when memory cells of the Nth layer of the YZ plane in the first group or the second group are programmed. 
     
     
       5. The program method of  claim 3 , wherein the bit lines are arranged to be vertical to the YZ plane and are divided into a first group and a second group, and the bit lines are activated by a group unit when memory cells of the Nth layer of the YZ plane are programmed. 
     
     
       6. The program method of  claim 3 , wherein, in the shadow programming method on each of the first and second groups, before upper bit data is programmed at memory cells at the Nth layer of the YZ plane, memory cells at a (N−1)th layer of the YZ plane are programmed by lower and upper bit data and memory cells at a (N+1)th layer of the YZ plane are programmed by lower bit data. 
     
     
       7. A method of programming a three dimensional nonvolatile memory device including a plurality of memory cells, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, each of the plurality of memory cells being a multi-bit memory cell that is configured to store least significant bit (LSB) data and most significant bit (MSB) data, the method comprising:
 programming the first memory cell with first LSB data and the second memory cell with second LSB data;   after programming the first memory cell with the first LSB data and the second memory cell with the second LSB data, programming the third memory cell with third LSB data and the fourth memory cell with fourth LSB data;   programming the first memory cell with first MSB data and the second memory cell with second MSB data; and   after programming the first memory cell with the first MSB data and the second memory cell with the second MSB data, programming the third memory cell with third MSB data and the fourth memory cell with fourth MSB data,   wherein the first memory cell and the second memory cell are connected to a first wordline,   the third memory cell and the fourth memory cell are connected to a second wordline,   the first memory cell and the third memory cell are included in a first string and stacked perpendicular to a substrate,   the second memory cell and the fourth memory cell are included in a second string and stacked perpendicular to the substrate, and   the first string and the second string are connected to a first bit line.    
     
     
       8. The method of claim 7, wherein the programming the first memory cell with first MSB data and the second memory cell with the second MSB data is performed before the programming the third memory cell with the third LSB data and the fourth memory cell with the fourth LSB data is performed.  
     
     
       9. The method of claim 8, wherein the programming the first memory cell with the first LSB data and the second memory cell with the second LSB data includes:
 programming the first memory cell with the first LSB data; and   programming the second memory cell with the second LSB data after the programming the first memory cell with the first LSB data.    
     
     
       10. The method of claim 9, wherein the programming the first memory cell with the first MSB data and the second memory cell with the second MSB data includes:
 programming the first memory cell with the first MSB data; and   programming the second memory cell with the second MSB data after the programming the first memory cell with the first MSB data.    
     
     
       11. The method of claim 7, wherein a third string and a fourth string are connected to the first bit line,
 the plurality of memory cells include a fifth memory cell and a sixth memory cell that are connected to the first wordline, the fifth memory cell being included in the third string, the sixth memory cell being included in the fourth string, and   programming the fifth memory cell with fifth LSB data and the sixth memory cell with sixth LSB data before the programming the third memory cell with the third LSB data and the fourth memory cell with the fourth LSB data.    
     
     
       12. The method of claim 7, wherein a first ground select transistor and a first string select transistor are included in the first string,
 a second ground select transistor and a second string select transistor are included in the second string,   the first string select transistor and the second string select transistor are connected to the first bit line,   the first memory cell and the third memory cell are positioned between the first ground select transistor and the first string select transistor,   the second memory cell and the fourth memory cell are positioned between the second ground select transistor and the second string select transistor,   a distance between the third memory cell and the first ground select transistor is greater than a distance between the first memory cell and the first ground select transistor, and   a distance between the fourth memory cell and the second ground select transistor is greater than a distance between the second memory cell and the second ground select transistor.    
     
     
       13. The method of claim 12, wherein the first ground select transistor and the second ground select transistor are connected to a first ground select line.  
     
     
       14. The method of claim 7, wherein the programming the first memory cell with first MSB data and the second memory cell with the second MSB data is performed after the programming the third memory cell with the third LSB data and the fourth memory cell with the fourth LSB data is performed.  
     
     
       15. A method of programming a three dimensional nonvolatile memory device including a plurality of memory cells, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, each of the plurality of memory cells being a multi-bit memory cell that is configured to store least significant bit (LSB) data and most significant bit (MSB) data, the method comprising:
 programming the first memory cell with first LSB data and first MSB data;   programming the second memory cell with second LSB data and second MSB data;   programming the third memory cell with third LSB data and third MSB data; and   programming the fourth memory cell with fourth LSB data and fourth MSB data,   wherein the third LSB data and the fourth LSB data are programmed after the first LSB data and the second LSB data,   the third MSB data and the fourth MSB data are programmed after the first MSB data and the second MSB data, and   the first MSB data and the second MSB data are programmed after the third LSB data and the fourth LSB data, and   wherein the first memory cell and the second memory cell are connected to a first wordline,   the third memory cell and the fourth memory cell are connected to a second wordline,   the first memory cell and the third memory cell are included in a first string and stacked perpendicular to a substrate,   the second memory cell and the fourth memory cell are included in a second string and stacked perpendicular to the substrate, and   the first string and the second string are connected to a first bit line.    
     
     
       16. The method of claim 15, wherein after the programming the first memory cell with the first LSB data, the programming the second memory cell with the second LSB data is performed.  
     
     
       17. The method of claim 15, wherein a third string and a fourth string are connected to the first bit line,
 the plurality of memory cells include a fifth memory cell and a sixth memory cell that are connected to the first wordline, the fifth memory cell being included in the third string, the sixth memory cell being included in the fourth string, and   programming the fifth memory cell with fifth LSB data and the sixth memory cell with sixth LSB data before the programming the third memory cell with the third LSB data and the fourth memory cell with the fourth LSB data.    
     
     
       18. The method of claim 15, wherein a first ground select transistor and a first string select transistor are included in the first string,
 a second ground select transistor and a second string select transistor are included in the second string,   the first string select transistor and the second string select transistor are connected to the first bit line,   the first memory cell and the third memory cell are positioned between the first ground select transistor and the first string select transistor,   the second memory cell and the fourth memory cell are positioned between the second ground select transistor and the second string select transistor,   a distance between the third memory cell and the first ground select transistor is greater than a distance between the first memory cell and the first ground select transistor, and   a distance between the fourth memory cell and the second ground select transistor is greater than a distance between the second memory cell and the second ground select transistor.    
     
     
       19. The method of claim 18, wherein the first ground select transistor and the second ground select transistor are connected to a first ground select line.  
     
     
       20. The method of claim 15, wherein the programming the first memory cell with the first MSB data and the second memory cell with the second MSB data includes:
 programming the first memory cell with the first MSB data; and   programming the second memory cell with the second MSB data after the programming the first memory cell with the first MSB data.    
     
     
       21. A method of operating a memory system including a three dimensional nonvolatile memory device and a controller, the three dimensional nonvolatile memory device including a plurality of memory cells, the plurality of memory cells including a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, each of the plurality of memory cells being a multi-bit memory cell that is configured to store two bit data, the method comprising:
 providing, by the controller, first through eighth page data to the three dimensional nonvolatile memory device, the first through eighth page data corresponding to a first through eighth addresses that gradually increase, first through eighth bit data being included in a corresponding one of the first through eighth page data;   programming the first cell and the second cell with the first through fourth bit data included in the first through fourth page data corresponding to the first through fourth addresses; and   after the programming the first cell and the second cell, programming the third cell and the fourth cell with the fifth through eighth bit data included in the fifth through eighth page data corresponding to the fifth through eighth addresses,   wherein the first memory cell and the second memory cell are connected to a first wordline,   the third memory cell and the fourth memory cell are connected to a second wordline,   the first memory cell and the third memory cell are included in a first string and stacked perpendicular to a substrate,   the second memory cell and the fourth memory cell are included in a second string and stacked perpendicular to the substrate, and   the first string and the second string are connected to a first bit line.    
     
     
       22. The method of claim 21, wherein a first ground select transistor and a first string select transistor are included in the first string,
 a second ground select transistor and a second string select transistor are included in the second string,   the first string select transistor and the second string select transistor are connected to the first bit line,   the first memory cell and the third memory cell are positioned between the first ground select transistor and the first string select transistor,   the second memory cell and the fourth memory cell are positioned between the second ground select transistor and the second string select transistor,   a distance between the third memory cell and the first ground select transistor is greater than a distance between the first memory cell and the first ground select transistor, and   a distance between the fourth memory cell and the second ground select transistor is greater than a distance between the second memory cell and the second ground select transistor.    
     
     
       23. The method of claim 22, wherein the first ground select transistor and the second ground select transistor are connected to a first ground select line.