USRE47640EExpiredUtilityPatentIndex 52

Semiconductor device

Assignee: TOSHIBA KKPriority: Feb 14, 2005Filed: Jan 5, 2017Granted: Oct 8, 2019

Est. expiryFeb 14, 2025(expired)· nominal 20-yr term from priority

Inventors:ICHIHARA REIKA TSUCHIYA YOSHINORI KOYAMA MASATO NISHIYAMA AKIRA

H01L 29/511H01L 21/823857H01L 29/51H01L 21/823462H01L 29/517H10D 84/0144H10D 64/691H10D 64/681H10D 64/68H10D 84/0181H10D 84/038

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Claims

Abstract

A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

Claims

exact text as granted — not AI-modified

The invention claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming an n-type semiconductor region and a p-type semiconductor region on a semiconductor substrate; forming a first gate dielectric layer above the n-type semiconductor region; forming a second gate dielectric layer above the p-type semiconductor region, the second gate dielectric layer having a composition different from that of the first gate dielectric layer; and forming a gate electrode layer over the n-type semiconductor region and the p-typesemiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, such that a portion of the first gate dielectric layer in contact with the gate electrode layer and a portion of the second gate dielectric layer in contact with the gate electrode layer include oxygen, a first element of at least one element selected from the group consisting of Zr, Hf, Ti, Ta, Nb, V, Sc, Y, a lanthanoide series and a actinide series, and said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region includes making the atomic density of the first element in the portion of the second gate dielectric layer be lower than the atomic density of the first element in the portion of the first gate dielectric layer.

2. The method according to claim 1 , wherein said forming a second gate dielectric layer includes forming the second gate dielectric layer with a second element including one selected from the group consisting of Al, Si and Ge.

3. The method according to claim 1 , further comprising:
removing the first gate dielectric layer on the p-type semiconductor region, after said forming a first gate dielectric layer and before said forming a second gate dielectric layer.

4. The method according to claim 3 , further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.

5. The method according to claim 4 , further comprising:
forming an insulating layer over the p-type semiconductor region and the n-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.

6. The method according to claim 1 , wherein said forming a second gate dielectric layer above the p-type semiconductor region includes forming the second gate dielectric layer above the p-type semiconductor region with the first gate dielectric layer interposed therebetween.

7. The method according to claim 6 , further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.

8. The method according to claim 7 , further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.

9. The method according to claim 6 , wherein said forming a second gate dielectric layer above the p-type semiconductor region includes forming the second gate dielectric layer so as to have a thickness of one or more mono layers and 2 nm or less.

10. The method according to claim 1 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χB−χA)×(d A +d B )≥3.9

is satisfied by electronegativity (χA) and an atomic radius (d A , a unit thereof is Å) of a metal element constituting the gate electrode layer and by electronegativity (χB) and an atomic radius (d B ) of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the first gate dielectric layer facing the gate electrode layer.

11. The method according to claim 10 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χC−χA)×(d A +d C )≤0.7

is satisfied, wherein χC and d C (a unit thereof is Å) are electronegativity and an atomic radius of an element having the highest binding energy to combine with the metal element constituting the gate electrode layer among elements constituting the portion of the second gate dielectric layer above the p-type semiconductor region facing the gate electrode layer.

12. The method according to claim 1 , wherein said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, includes making the atomic density of the first element contained in the second gate dielectric layer be 50% or less of atomic density of the first element contained in the first gate dielectric layer.

13. The method according to claim 1 , wherein said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, includes making a portion of the first gate electrode layer in contact with the first gate dielectric layer and a portion of the second gate electrode layer in contact with the second gate dielectric layer include the same metal element.

14. The method according to claim 1 , wherein said forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, includes making a portion of the first gate electrode layer in contact with the first gate dielectric layer and a portion of the second gate electrode layer in contact with the second pate dielectric layer include at least one metal element selected from the group consisting of Ta, La, Er, Zr, Hf, Ti and La.

15. A method of manufacturing a semiconductor device, comprising:
forming an n-type semiconductor region and a p-type semiconductor region on a semiconductor substrate; forming a second gate dielectric layer above the n-type semiconductor region and the p-type semiconductor region; forming a first gate dielectric layer above the n-type semiconductor region, the first gate dielectric layer being made of an insulating material different from that of the second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer being formed of an oxide layer including a first element of at least one metal element selected from the group consisting of Zr, Hf, Ti, Ta, Nb, V, Sc, Y, a lanthanoide series and a actinide series; and forming a gate electrode layer over the n-type semiconductor region and the p-type semiconductor region, after said forming a first gate dielectric layer and said forming a second gate dielectric layer, wherein an atomic density of the first element in a portion of the second pate dielectric layer in contact with the gate electrode layer is lower than an atomic density of the first element in a portion of the first pate dielectric layer in contact with the gate electrode layer.

16. The method according to claim 15 , wherein said forming a second gate dielectric layer includes forming the second gate dielectric layer with a material including one selected from the group consisting of Al, Si and Ge.

17. The method according to claim 15 , wherein said forming a first gate dielectric layer above the n-type semiconductor region includes forming the first gate dielectric layer above the n-type semiconductor region with the second gate dielectric layer interposed therebetween.

18. The method according to claim 17 , further comprising:
forming a first gate electrode above the n-type semiconductor region and a second gate electrode above the p-type semiconductor region, by selectively etching the gate electrode layer.

19. The method according to claim 18 , further comprising:
forming an insulating layer over the n-type semiconductor region and the p-type semiconductor region to bury the first gate electrode and the second gate electrode, after said forming the first gate electrode and the second gate electrode; and flatly etching back the insulating layer to expose tops of the first gate electrode and the second gate electrode.

20. The method according to claim 17 , wherein said forming a first gate dielectric layer above the n-type semiconductor region includes forming the first gate dielectric layer so as to have a thickness of one or more mono layers and 2 nm or less.

21. The method according to claim 15 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χB−χA)×(d A +d B )≥3.9

22. The method according to claim 21 , wherein said forming a gate electrode layer includes forming the gate electrode layer such that a relation:
(χC−χA)×(d A +d C )≤0.7

23. A semiconductor device comprising:
a semiconductor substrate; an nMISFET including a first dielectric layer disposed above the semiconductor substrate and a first metal gate electrode formed on the first dielectric layer; and a pMISFET including a second dielectric layer disposed above the semiconductor substrate and a second metal gate electrode formed on the second dielectric layer, wherein a portion of the first dielectric layer contains oxygen and hafnium, a portion of the second dielectric layer contains oxygen and hafnium, and the atomic density of aluminum in the second dielectric layer is lower than the atomic density of aluminum in the first dielectric layer.

24. The semiconductor device according to claim 23, wherein the portions of the first and second dielectric layers containing oxygen and hafnium further include titanium.

25. The semiconductor device according to claim 24, wherein the portion of the second dielectric layer containing oxygen and hafnium is in direct contact with the second metal gate electrode.

26. The semiconductor device according to claim 25, wherein the portion of the second dielectric layer containing oxygen and hafnium further includes nitrogen.

27. The semiconductor device according to claim 24, wherein the portions of the first and second dielectric layers containing oxygen and hafnium further include nitrogen.

28. The semiconductor device according to claim 24, wherein the first dielectric layer includes a sub-layer contacting the first metal gate electrode and the sub-layer contains aluminum and nitrogen.

29. The semiconductor device according to claim 24, wherein
the portion of the first dielectric layer containing oxygen and hafnium has a thickness of 2 nm or less in the location between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric layer containing oxygen and hafnium has a thickness of 2 nm or less in the location between the semiconductor substrate and the second metal gate electrode.

30. The semiconductor device according to claim 24, wherein the portion of the second dielectric layer containing oxygen and hafnium includes tantalum.

31. The semiconductor device according to claim 30, wherein the atomic density of tantalum in the portion of the first dielectric layer containing oxygen and hafnium is lower than the atomic density of tantalum in the portion of the second dielectric layer containing oxygen and hafnium.

32. The semiconductor device according to claim 24, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

33. The semiconductor device according to claim 24, wherein the first metal gate electrode includes titanium and the second metal gate electrode includes titanium.

34. The semiconductor device according to claim 23, wherein the portions of the first and second dielectric layers containing oxygen and hafnium further include nitrogen.

35. The semiconductor device according to claim 34, wherein the first dielectric layer includes a sub-layer containing aluminum and nitrogen in contact with the first metal gate electrode.

36. The semiconductor device according to claim 34, wherein
the portion of the first dielectric layer containing oxygen and hafnium has a thickness of 2 nm or less in the location between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric layer containing oxygen and hafnium has a thickness of 2 nm or less in the location between the semiconductor substrate and the second metal gate electrode.

37. The semiconductor device according to claim 34, wherein the portion of the second dielectric layer containing oxygen and hafnium further includes tantalum.

38. The semiconductor device according to claim 37, wherein the atomic density of tantalum in the portion of the first dielectric layer containing oxygen and hafnium is lower than the atomic density of tantalum in the portion of the second dielectric layer containing oxygen and hafnium.

39. The semiconductor device according to claim 23, wherein the first dielectric layer includes a sub-layer containing aluminum and nitrogen contacting the first metal gate.

40. The semiconductor device according to claim 39, wherein the second dielectric layer comprises a layer of silicon oxide (SiO 2 ) located between the semiconductor substrate and the portion thereof containing oxygen and hafnium.

41. The semiconductor device according to claim 39, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

42. The semiconductor device according to claim 39, wherein the atomic density of aluminum in the second dielectric layer is 50% or less of the atomic density of aluminum in the first dielectric layer.

43. The semiconductor device according to claim 23, wherein
the portion of the first dielectric layer containing oxygen and hafnium has a thickness of 2 nm or less in the location between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric containing oxygen and hafnium layer has a thickness of 2 nm or less in the location between the semiconductor substrate and the second metal gate electrode.

44. The semiconductor device according to claim 23, wherein the second dielectric layer comprises a layer of silicon oxide (SiO 2 ) located between the semiconductor substrate and the portion thereof containing oxygen and hafnium.

45. The semiconductor device according to claim 23, wherein the portion of the second dielectric layer containing oxygen and hafnium further includes tantalum.

46. The semiconductor device according to claim 45, wherein the atomic density of tantalum in the portion of the first dielectric layer containing oxygen and hafnium is lower than the atomic density of tantalum in the portion of the second dielectric layer containing oxygen and hafnium.

47. The semiconductor device according to claim 46, wherein the first metal gate electrode includes titanium and the second metal gate electrode includes titanium.

48. The semiconductor device according to claim 45, wherein the first metal gate electrode includes titanium and the second metal gate electrode includes titanium.

49. The semiconductor device according to claim 23, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

50. The semiconductor device according to claim 23, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

51. The semiconductor device according to claim 23, wherein the atomic density of aluminum in the second dielectric layer is 50% or less of the atomic density of aluminum in the first dielectric layer.

52. The semiconductor device according to claim 23, wherein the first metal gate electrode includes titanium and the second metal gate electrode includes titanium.

53. A semiconductor device comprising:
a semiconductor substrate; an nMISFET including a first dielectric layer disposed above the semiconductor substrate and a first metal gate electrode formed on the first dielectric layer; and a pMISFET including a second dielectric layer disposed above the semiconductor substrate and a second metal gate electrode formed on the second dielectric layer, wherein a portion of the first dielectric layer comprises oxygen and hafnium and a portion of the second dielectric layer comprises oxygen and hafnium, and the atomic density of tantalum in the portion of the first dielectric layer is lower than the atomic density of tantalum in the portion of the second dielectric layer.

54. The semiconductor device according to claim 53, wherein the atomic density of tantalum in the portion of the first dielectric layer comprising oxygen and hafnium is 50% or less of the atomic density of tantalum in the second dielectric layer.

55. The semiconductor device according to claim 54, wherein the portion of the second dielectric layer comprising oxygen and hafnium further includes titanium.

56. The semiconductor device according to claim 55, wherein the first metal gate electrode and the second metal gate electrode include titanium.

57. The semiconductor device according to claim 55, wherein the portion of the first dielectric layer comprising oxygen and hafnium further includes nitrogen.

58. The semiconductor device according to claim 55, wherein
the portion of the first dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the second metal gate electrode.

59. The semiconductor device according to claim 54, wherein the portion of the first dielectric layer comprising oxygen and hafnium includes nitrogen.

60. The semiconductor device according to claim 54, wherein
the portion of the first dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the second metal gate electrode.

61. The semiconductor device according to claim 53, wherein the portion of the second dielectric comprising oxygen and hafnium layer includes titanium.

62. The semiconductor device according to claim 61, wherein the portion of the first dielectric layer comprising oxygen and hafnium includes nitrogen.

63. The semiconductor device according to claim 62, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

64. The semiconductor device according to claim 61, wherein the first dielectric layer further comprises a sub-layer of silicon oxide (SiO 2 ) between the semiconductor substrate and the portion of the first dielectric comprising oxygen and hafnium.

65. The semiconductor device according to claim 61, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

66. The semiconductor device according to claim 53, wherein the first metal gate electrode and the second metal gate electrode include titanium.

67. The semiconductor device according to claim 66, wherein the portion of the first dielectric layer comprising oxygen and hafnium further includes nitrogen.

68. The semiconductor device according to claim 53, wherein the portion of the first dielectric layer comprising oxygen and hafnium further includes nitrogen.

69. The semiconductor device according to claim 68, wherein
the portion of the first dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the second metal gate electrode.

70. The semiconductor device according to claim 53, wherein
the portion of the first dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the first metal gate electrode, and the portion of the second dielectric layer comprising oxygen and hafnium has a thickness of 2 nm or less between the semiconductor substrate and the second metal gate electrode.

71. The semiconductor device according to claim 70, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

72. The semiconductor device according to claim 53, wherein the first dielectric layer further comprises a sub-layer of silicon oxide (SiO 2 ) between the semiconductor substrate and the portion of the first dielectric comprising oxygen and hafnium.

73. The semiconductor device according to claim 53, further comprising a tungsten metal layer formed on each of the first metal gate electrode and the second metal gate electrode.

74. A method of manufacturing a semiconductor device, comprising:
forming an nMISFET including a first dielectric layer disposed above a semiconductor substrate and a first metal gate electrode formed on the first dielectric layer; and forming a pMISFET including a second dielectric layer disposed above the semiconductor substrate and a second metal gate electrode formed on the second dielectric layer, wherein a portion of the first dielectric layer contains oxygen and hafnium and a portion of the second dielectric layer contains oxygen and hafnium, and the atomic density of aluminum in the second dielectric layer is lower than the atomic density of aluminum in the first dielectric layer.

75. The method according to claim 74, wherein the portion of the first dielectric layer comprising oxygen and hafnium and the portion of the second dielectric layer comprising oxygen and hafnium each include titanium.

76. The method according to claim 74, wherein the portion of the first dielectric layer comprising oxygen and hafnium and the portion of the second dielectric layer comprising oxygen and hafnium each include nitrogen.

77. The method according to claim 74, wherein the first dielectric layer includes a sub-layer contacting the first metal gate electrode and the sub-layer contains aluminum and nitrogen.

78. The method according to claim 74, wherein the second dielectric layer further comprises a sub-layer of silicon oxide (SiO 2 ) between the semiconductor substrate and the portion of the second dielectric layer containing oxygen and hafnium.

79. The method according to claim 74, wherein the portion of the second dielectric layer comprising oxygen and hafnium includes tantalum.

80. The method according to claim 79, wherein the atomic density of tantalum in the portion of the first dielectric comprising oxygen and hafnium is lower than the atomic density of tantalum in the portion of the second dielectric layer comprising oxygen and hafnium.

81. The method according to claim 74, wherein the portion of the second dielectric comprising oxygen and hafnium is formed by atomic layer deposition.

82. The method according to claim 81, wherein the first metal gate electrode and the second metal gate electrode are formed by a damascene process.

83. The method according to claim 74, wherein the first metal gate electrode and the second metal gate electrode are formed by a damascene process.

84. A method of manufacturing a semiconductor device, comprising:
forming an nMISFET including a first dielectric layer disposed above a semiconductor substrate and a first metal gate electrode formed on the first dielectric layer; and forming a pMISFET including a second dielectric layer disposed above the semiconductor substrate and a second metal gate electrode formed on the second dielectric layer, wherein a portion of the first dielectric layer contacting the first metal gate electrode and a portion of the second dielectric layer contacting the second metal gate electrode each comprise oxygen and hafnium and, an atomic density of tantalum in the portion of the first dielectric layer is lower than an atomic density of tantalum in the portion of the second dielectric layer.

85. The method according to claim 84, wherein the atomic density of tantalum in the portion of the first dielectric layer comprising oxygen and hafnium is 50% or less of an atomic density of tantalum in the second dielectric layer.

86. The method according to claim 84, wherein the portion of the first dielectric layer comprising oxygen and hafnium and the portion of the second dielectric layer comprising oxygen and hafnium further include titanium.

87. The method according to claim 84, wherein the portion of the first dielectric layer comprising oxygen and hafnium and the portion of the second dielectric layer comprising oxygen and hafnium further include nitrogen.

88. The method according to claim 84, wherein the portion of the first dielectric layer comprising oxygen and hafnium is formed by atomic layer deposition.

89. The method according to claim 88, wherein the first metal gate electrode and the second metal gate electrode are formed with a damascene process.

90. The method according to claim 84, wherein the first metal gate electrode and the second metal gate electrode are formed with a damascene process.

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