3D flash memory device having different dummy word lines utilized during erase operations

Abstract

A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

What is claimed is: 
     
       1. A three-dimensional (3D) flash memory device comprising:
 a plurality of cell strings arranged, each of the plurality of cell strings including a string select transistor, first and second dummy transistors, a plurality of memory cells, third and fourth dummy transistors and a ground select transistor stacked in a direction perpendicular to a substrate;   a dummy word line voltage generator configured to provide a first voltage to a first dummy word line connected to the first dummy transistor, a second voltage to a second dummy word line connected to the second dummy transistor, a third voltage to a third dummy word line connected to the third dummy transistor, and a fourth voltage to a fourth dummy word line connected to the fourth dummy transistor during an erase operation; and   a word line voltage generator configured to apply a fifth voltage to a plurality of main word lines connected to the plurality of memory cells respectively during the erase operation,   wherein the second dummy transistor and the third dummy transistor are disposed between the first dummy transistor and the fourth dummy transistor, the second voltage and the third voltage are the same, and the second voltage is different from the first voltage and the fourth voltage.   
     
     
       2. The 3D flash memory device of  claim 1 , wherein the first dummy transistor is adjacent to the string select transistor, the plurality of memory cells is disposed between the second dummy transistor and the third dummy transistor, and the fourth dummy transistor is adjacent to the ground select transistor. 
     
     
       3. The 3D flash memory device of  claim 1 , further comprising:
 an erase voltage generator configured to provide an erase voltage to the substrate during the erase operation.   
     
     
       4. The 3D flash memory device of  claim 1 , wherein the string select transistor, the first and second dummy transistors, the plurality of memory cells, the third and fourth dummy transistors and the ground select transistor of each of the cell strings share a channel perpendicular to the substrate. 
     
     
       5. The 3D flash memory device of  claim 1 , wherein memory cells having a same height from the substrate share a main word line among the plurality of main word lines. 
     
     
       6. The 3D flash memory device of  claim 1 , wherein the second voltage is lower than the first voltage. 
     
     
       7. The 3D flash memory device of  claim 6 , wherein the word line voltage generator is configured to apply a sixth voltage that is higher than the second voltage to a string select line connected to the string select transistor. 
     
     
       8. The 3D flash memory device of  claim 1 , wherein the fourth voltage is applied after the second voltage is applied. 
     
     
       9. The 3D flash memory device of  claim 1 , further comprising:
 a fifth dummy transistor that is located between the first dummy transistor and the second dummy transistor.   
     
     
       10. A method of performing an erase operation of a three-dimensional (3D) flash memory device, the 3D flash memory device comprising a plurality of cell strings, each of the plurality of cell strings including a string select transistor, first and second dummy transistors, a plurality of memory cells, third and fourth dummy transistors and a ground select transistor stacked in a direction perpendicular to a substrate, the second dummy transistor and the third dummy transistor disposed between the first dummy transistor and the fourth dummy transistor, the method comprising:
 applying an erase voltage to the substrate;   applying a first voltage to a first dummy word line connected to the first dummy transistor;   applying a second voltage to a second dummy word line connected to the second dummy transistor;   applying a third voltage to a third dummy word line connected to the third dummy transistor;   applying a fourth voltage to a fourth dummy word line connected to the fourth dummy transistor; and   applying a fifth voltage to a plurality of main word lines connected to the plurality of memory cells,   wherein the second voltage and the third voltage are the same, and the second voltage is different from the first voltage and the fourth voltage.   
     
     
       11. The method of  claim 10 , wherein the first dummy transistor is adjacent to the string select transistor, the plurality of memory cells is disposed between the second dummy transistor and the third dummy transistor, and the fourth dummy transistor is adjacent to the ground select transistor. 
     
     
       12. The method of  claim 11 , wherein the second voltage is lower than the first voltage. 
     
     
       13. The method of  claim 12 , further comprising:
 applying a sixth voltage that is higher than the second voltage to a string select line connected to the string select transistor.   
     
     
       14. The method of  claim 13 , further comprising:
 applying a seventh voltage to a fifth dummy word line connected to a fifth dummy transistor, wherein the fifth dummy transistor is located between the first dummy transistor and the second dummy transistor.   
     
     
       15. The method of  claim 14 , wherein the fourth voltage is applied after the second voltage is applied. 
     
     
       16. A data storage device comprising:
 a three-dimensional (3D) flash memory device comprising a plurality of memory blocks, each of the plurality of memory blocks including a plurality of cell strings, each of the plurality of cell strings including a string select transistor, first and second dummy transistors, a plurality of memory cells, third and fourth dummy transistors and a ground select transistor stacked in a direction perpendicular to a substrate; and   a controller configured to transmit an erase command and an address indicating a selected memory block among the plurality of memory blocks to the 3D flash memory device,   wherein the 3D flash memory device further comprises:   a dummy word line voltage generator configured to provide a first voltage to a first dummy word line connected to the first dummy transistor, a second voltage to a second dummy word line connected to the second dummy transistor, a third voltage to a third dummy word line connected to the third dummy transistor, and a fourth voltage to a fourth dummy word line connected to the fourth dummy transistor during an erase operation; and   a word line voltage generator configured to apply a fifth voltage to a plurality of main word lines connected to the plurality of memory cells respectively during the erase operation,   wherein the second dummy transistor and the third dummy transistor are disposed between the first dummy transistor and the fourth dummy transistor, the second voltage and the third voltage are the same, and the second voltage is different from the first voltage and the fourth voltage.   
     
     
       17. The data storage device of  claim 16 , wherein string select transistors in cell strings among the plurality of cell strings arranged in different rows are connected to different string select lines in each of the plurality of memory blocks, and
 string select transistors in cell strings among the plurality of cell strings arranged in a same row are connected to a same string select line in each of the plurality of memory blocks.   
     
     
       18. The data storage device of  claim 16 , wherein string select transistors in cell strings among the plurality of cell strings arranged in different columns are connected to different bit lines in each of the plurality of memory blocks, and
 string select transistors in cell strings among the plurality of cell strings arranged in a same column are connected to a same bit line in each of the plurality of memory blocks.   
     
     
       19. The data storage device of  claim 16 ,
 wherein the first dummy transistor is adjacent to the string select transistor, the plurality of memory cells is disposed between the second dummy transistor and the third dummy transistor, and the fourth dummy transistor is adjacent to the ground select transistor,   wherein the second voltage is lower than the first voltage.   
     
     
       20. The data storage device of  claim 16 ,
 wherein the word line voltage generator is configured to apply a sixth voltage that is higher than the second voltage to a string select line connected to the string select transistor.   
     
     
       21. A three-dimensional (3D) flash memory device comprising:
 a plurality of cell strings, a cell string of the plurality of cell strings being connected between a common source line and a bit line and including a ground select transistor, at least one first dummy memory cell, a plurality of memory cells, at least two second dummy memory cells and a string select transistor being sequentially stacked along a direction perpendicular to a substrate;   wherein the ground select transistor is connected to a ground select line, the at least one first dummy memory cell is connected to at least one first dummy word line, the plurality of memory cells are connected to a plurality of word lines respectively, the at least two second dummy memory cells are connected to at least two second dummy word lines respectively, the string select transistor is connected to a string select line,   wherein the ground select transistor is adjacent to the substrate and the string select transistor is adjacent to the bit line,   wherein the at least one first dummy word line is disposed between the ground select line and the plurality of word lines and adjacent to lowermost word line of the plurality of word lines, the at least two second dummy word lines is disposed between the string select line and the plurality of word lines and adjacent to uppermost word line of the plurality of word lines,   wherein a first separation length between the ground select line and the at least one first dummy word line is different from a second separation length between the string select line and one second dummy word line, among the at least two second dummy word lines, most adjacent to the string select line, and   wherein a third separation length between the ground select line and a first word line, among the plurality of word lines, most adjacent to the ground select line is different from a fourth separation length between the string select line and a second word line, among the plurality of word lines, most adjacent to the string select line,   a dummy word line voltage generator configured to provide at least one first voltage to the at least one first dummy word line and provide at least two second voltages to the at least two second dummy word lines during an erase operation;   a word line voltage generator configured to apply third voltages to the plurality of word lines during the erase operation.    
     
     
       22. The 3D flash memory device of claim 21, further comprising:
 an erase voltage generator configured to generate an erase voltage applied to the substrate during the erase operation;   a select line voltage generator configured to generate a string select line voltage applied to the string select line and a ground select line voltage applied to the ground select line;   a program voltage generator configured to generate a program voltage applied to a select word line among the plurality of word lines during a program operation; and   a pass voltage generator configured to generate pass voltages applied to the plurality of word lines during the program operation.    
     
     
       23. The 3D flash memory device of claim 21, further comprising:
 a control logic circuit configured to receive a command and an address via an arrangement of input and output lines and receive a control signal via designated control lines from an external device;   a data input and output circuit configured to receive or output data via the arrangement of input and output lines from or to the external device;   a page buffer circuit connected to the plurality of cell strings via a plurality of bit lines and configured to receive or output the data from or to the data input and output circuit, and temporarily store the data to be programmed to or the data read from selected memory cells of the plurality of cell strings during a program or read operation; and   an address decoder connected to the plurality of word lines, the at least one first dummy word line and the at least two second dummy word line, configured to receive the at least one first voltage and the at least two second voltages from the dummy word line voltage generator and the third voltages from the word line voltage generator, and configured to apply the at least one first voltage to the at least one first dummy word line, apply the at least two second voltage to the at least two dummy word lines, and apply the third voltages to the plurality of word lines during the erase operation under a control of the control logic circuit,   wherein the dummy word line voltage generator is configured to receive a power supply voltage via power supply lines from the external device and generate the at least one first voltages and the at least two second voltage from the power supply voltage,   wherein the word line voltage generator is configured to receive the power supply voltage via the power supply lines from the external device and generate the third voltages from the power supply voltage.    
     
     
       24. The 3D flash memory device of claim 21, wherein the at least two second voltages are different each other during the erase operation.  
     
     
       25. A three-dimensional (3D) flash memory device comprising:
 a plurality of cell strings, a cell string of the plurality of cell strings being connected between a common source line and a bit line and including a ground select transistor, at least one first dummy memory cell, a plurality of memory cells, at least two second dummy memory cells and a string select transistor being sequentially stacked along a direction perpendicular to a substrate;   wherein the ground select transistor is connected to a ground select line, the at least one first dummy memory cell is connected to at least one first dummy word line, the plurality of memory cells are connected to a plurality of word lines respectively, the at least two second dummy memory cells are connected to at least two second dummy word lines respectively, the string select transistor is connected to a string select line,   wherein the ground select transistor is adjacent to the substrate and the string select transistor is adjacent to the bit line,   wherein the at least one first dummy word line is disposed between the ground select line and the plurality of word lines and adjacent to lowermost word line of the plurality of word lines, the at least two second dummy word lines is disposed between the string select line and the plurality of word lines and adjacent to uppermost word line of the plurality of word lines,   wherein a first separation length between the ground select line and the at least one first dummy word line is different from a second separation length between the string select line and one second dummy word line, among the at least two second dummy word lines, most adjacent to the string select line, and   wherein a third separation length between the ground select line and a first word line, among the plurality of word lines, most adjacent to the ground select line is different from a fourth separation length between the string select line and a second word line, among the plurality of word lines, most adjacent to the string select line;   a dummy word line voltage generator configured to provide at least one first voltage to the at least one first dummy word line and provide at least two second voltages to the at least two second dummy word lines during a program operation;   a word line voltage generator configured to receive a power supply voltage via power supply lines from an external device and provide third voltages to the plurality of word lines during the program operation.    
     
     
       26. The 3D flash memory device of claim 25, further comprising:
 a control logic circuit configured to receive a command and an address via an arrangement of input and output lines and receive a control signal via designated control lines from the external device;   a data input and output circuit configured to receive or output data via the arrangement of input and output lines from or to the external device;   a page buffer circuit connected to the plurality of cell strings via a plurality of bit lines and configured to receive or output the data from or to the data input and output circuit, and temporarily store the data to be programmed to or the data read from selected memory cells of the plurality of cell strings during a program or read operation;   an address decoder connected to the plurality of word lines, the at least one first dummy word line and the at least two second dummy word line, configured to receive the at least one first voltage and the at least two second voltages from the dummy word line voltage generator and the third voltages from the word line voltage generator, and configured to apply the at least one first voltage to the at least one first dummy word line, apply the at least two second voltage to the at least two dummy word lines, and apply the third voltages to the plurality of word lines during the program operation under a control of the control logic circuit;   an erase voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate an erase voltage applied to the substrate from the power supply voltage during an erase operation; and   a select line voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate a string select line voltage applied to the string select line and a ground select line voltage applied to the ground select line from the power supply voltage,   wherein the third voltage includes a program voltage and pass voltages,   wherein the word line voltage generator comprises:
 a program voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate the program voltage applied to a select word line among the plurality of word lines from the power supply voltage during the program operation; and 
 a pass voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate the pass voltages applied to the plurality of word lines from the power supply voltage during the program operation.  
   
     
     
       27. The 3D flash memory device of claim 26, wherein the at least two second voltages are different each other during the erase operation,
 wherein the program voltage and the pass voltage are high voltages higher than the power supply voltage.    
     
     
       28. A three-dimensional (3D) flash memory device comprising:
 a plurality of cell strings, a cell string of the plurality of cell strings being connected between a common source line and a bit line and including a ground select transistor, at least one first dummy memory cell, a plurality of memory cells, at least two second dummy memory cells and a string select transistor being sequentially stacked along a direction perpendicular to a substrate;   wherein the ground select transistor is connected to a ground select line, the at least one first dummy memory cell is connected to at least one first dummy word line, the plurality of memory cells are connected to a plurality of word lines respectively, the at least two second dummy memory cells are connected to at least two second dummy word lines respectively, the string select transistor is connected to a string select line,   wherein the ground select transistor is adjacent to the substrate and the string select transistor is adjacent to the bit line,   wherein the at least one first dummy word line is disposed between the ground select line and the plurality of word lines and adjacent to lowermost word line of the plurality of word lines, the at least two second dummy word lines is disposed between the string select line and the plurality of word lines and adjacent to uppermost word line of the plurality of word lines,   wherein a first separation length between the ground select line and the at least one first dummy word line is different from a second separation length between the string select line and one second dummy word line, among the at least two second dummy word lines, most adjacent to the string select line, and   wherein a third separation length between the ground select line and a first word line, among the plurality of word lines, most adjacent to the ground select line is different from a fourth separation length between the string select line and a second word line, among the plurality of word lines, most adjacent to the string select line,   a dummy word line voltage generator configured to provide at least one first voltage to the at least one first dummy word line and provide at least two second voltages to the at least two second dummy word lines during an erase operation;   a word line voltage generator configured to apply third voltages to the plurality of word lines during the erase operation,   wherein the dummy word line voltage generator is further configured to provide at least one fourth voltage to the at least one first dummy word line and provide at least two fifth voltages to the at least two second dummy word lines during a program operation, and   wherein the word line voltage generator is further configured to apply a sixth voltages to the plurality of word lines during the program operation.    
     
     
       29. The 3D flash memory device of claim 28, further comprising:
 a control logic circuit configured to receive a command and an address via an arrangement of input and output lines and receive a control signal via designated control lines from an external device;   a data input and output circuit configured to receive or output data via the arrangement of input and output lines from or to the external device;   a page buffer circuit connected to the plurality of cell strings via a plurality of bit lines and configured to receive or output the data from or to the data input and output circuit, and temporarily store the data to be programmed to or the data read from selected memory cells of the plurality of cell strings during a program or read operation;   an address decoder connected to the plurality of word lines, the at least one first dummy word line and the at least two second dummy word line, configured to receive the at least one first voltage and the at least two second voltages from the dummy word line voltage generator and the third voltages from the word line voltage generator, and configured to apply the at least one first voltage to the at least one first dummy word line, apply the at least two second voltage to the at least two dummy word lines, and apply the third voltages to the plurality of word lines during the erase operation under a control of the control logic circuit;   an erase voltage generator configured to receive a power supply voltage via power supply lines from the external device and generate an erase voltage applied to the substrate from the power supply voltage during the erase operation; and   a select line voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate a string select line voltage applied to the string select line and a ground select line voltage applied to the ground select line from the power supply voltage,   wherein the address decoder is further configured to receive the at least one fourth voltage and the at least two fifth voltages from the dummy word line voltage generator and the sixth voltages from the word line voltage generator, and configured to apply the at least one fourth voltage to the at least one first dummy word line, apply the at least two fifth voltage to the at least two dummy word lines, and apply the sixth voltages to the plurality of word lines during the program operation under the control of the control logic circuit,   wherein the sixth voltages includes a program voltage and pass voltages,   wherein the word line voltage generator comprises:
 a program voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate the program voltage applied to a select word line among the plurality of word lines from the power supply voltage during the program operation; and 
 a pass voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate the pass voltage applied to the plurality of word lines from the power supply voltage during the program operation, 
   wherein the at least two second voltages are different each other during the erase operation,   wherein the program voltage and the pass voltage are high voltages higher than the power supply voltage.    
     
     
       30. A method of erasing a three-dimensional (3D) flash memory device comprising a plurality of cell strings and a voltage generator, the method comprising:
 applying, by the voltage generator, a first voltage to word lines connected to a plurality of memory cells of the plurality of cell strings, each cell string comprising a set of memory cells, from among the plurality of memory cells, stacked in a direction perpendicular to a substrate;   applying, by the voltage generator, a second voltage to a first dummy word line connected to first dummy transistors of the plurality of cell strings, each first dummy transistor being above the set of the memory cells in each cell string in the direction perpendicular to the substrate;   applying, by the voltage generator, a third voltage to a second dummy word line connected to second dummy transistors of the plurality of cell strings, each second dummy transistor being between the first dummy transistor and the set of the memory cells in each cell string in the direction perpendicular to the substrate;   applying, by the voltage generator, a fourth voltage to a third dummy word line connected to third dummy transistors of the plurality of cell strings, each third dummy transistor being between the set of the memory cells and the substrate in each cell string in the direction perpendicular to the substrate;   applying, by the voltage generator, a fifth voltage to a fourth dummy word line connected to fourth dummy transistors of the plurality of cell strings, each third dummy transistor being between the third dummy transistor and the substrate in each cell string in the direction perpendicular to the substrate,   wherein the third voltage is different from the second voltage.    
     
     
       31. The method of claim 30, wherein a string select transistor is above the first dummy transistor in the direction perpendicular to the substrate, and a ground select transistor is between the fourth dummy transistor and the substrate in each cell string in the direction perpendicular to the substrate.  
     
     
       32. The method of claim 30, further comprising:
 applying an erase voltage to the substrate during an erase operation.    
     
     
       33. The method of claim 32, wherein the fifth voltage is applied after the erase voltage is applied to the substrate.  
     
     
       34. The method of claim 31, wherein the string select transistor, the first and second dummy transistors, the plurality of memory cells, the third and fourth dummy transistors and the ground select transistor of each of the cell strings share a channel perpendicular to the substrate.  
     
     
       35. The method of claim 30, wherein memory cells having a same height from the substrate share a main word line among a plurality of main word lines.  
     
     
       36. The method of claim 30, wherein the third voltage is lower than the second voltage.  
     
     
       37. The method of claim 30, further comprising:
 applying a sixth voltage that is higher than the second voltage to string select lines connected to string select transistors of the plurality of cell strings, each string select transistor being above the first dummy transistor in each cell string in the direction perpendicular to the substrate.    
     
     
       38. The method of claim 30, further comprising:
 applying a sixth voltage to a fifth dummy word line connected to a fifth dummy memory cells of the plurality of cell strings, each fifth dummy transistor being located between the first dummy transistor and the second dummy transistor in the direction perpendicular to the substrate.    
     
     
       39. A method of performing an operation of a three-dimensional (3D) flash memory device comprising a plurality of cell strings and a voltage generator, the method comprising:
 applying, by the voltage generator, at least one first voltage to at least one first dummy word line;   applying, by the voltage generator, at least two second voltages to at least two second dummy word lines respectively; and   applying, by the voltage generator, a plurality of third voltages to a plurality of word lines respectively,   wherein the 3D flash memory device comprises a plurality of cell strings, a cell string of the plurality of cell strings being connected between a common source line and a bit line and including a ground select transistor, at least one first dummy memory cell, a plurality of memory cells, at least two second dummy memory cells and a string select transistor being sequentially stacked along a direction perpendicular to a substrate,   wherein the ground select transistor is connected to a ground select line, the at least one first dummy memory cell is connected to the at least one first dummy word line, the plurality of memory cells are connected to the plurality of word lines respectively, the at least two second dummy memory cells are connected to the at least two second dummy word lines respectively, the string select transistor is connected to a string select line,   wherein the ground select transistor is adjacent to the substrate and the string select transistor is adjacent to the bit line,   wherein the at least one first dummy word line is disposed between the ground select line and the plurality of word lines and adjacent to lowermost word line of the plurality of word lines, the at least two second dummy word lines is disposed between the string select line and the plurality of word lines and adjacent to uppermost word line of the plurality of word lines,   wherein a first separation length between the ground select line and the at least one first dummy word line is different from a second separation length between the string select line and one second dummy word line, among the at least two second dummy word lines, most adjacent to the string select line, and   wherein a third separation length between the ground select line and a first word line, among the plurality of word lines, most adjacent to the ground select line is different from a fourth separation length between the string select line and a second word line, among the plurality of word lines, most adjacent to the string select line.    
     
     
       40. The method of claim 39, wherein the 3D flash memory further comprises:
 a control logic circuit configured to receive a command and an address via an arrangement of input and output lines and receive a control signal via designated control lines from an external device;   a data input and output circuit configured to receive or output data via the arrangement of input and output lines from or to the external device;   a page buffer circuit connected to the plurality of cell strings via a plurality of bit lines and configured to receive or output the data from or to the data input and output circuit, and temporarily store the data to be programmed to or the data read from selected memory cells of the plurality of cell strings during a program or read operation;   an address decoder connected to the plurality of word lines, the at least one first dummy word line and the at least two second dummy word line, configured to receive the at least one first voltage and the at least two second voltages from the dummy word line voltage generator and the plurality of third voltages from the word line voltage generator, and configured to apply the at least one first voltage to the at least one first dummy word line, apply the at least two second voltage to the at least two dummy word lines, and apply the plurality of third voltages to the plurality of word lines under a control of the control logic circuit,   wherein the voltage generator comprises:
 an erase voltage generator configured to receive a power supply voltage via power supply lines from the external device and generate an erase voltage applied to the substrate from the power supply voltage during an erase operation; 
 a word line voltage generator configured to receive the power supply voltage via power supply lines from the external device and generate the plurality of third voltages from the power supply voltage; 
 a dummy word line voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate the at least one first voltage and the at least two second voltages from the power supply voltage; 
 a select line voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate a string select line voltage applied to the string select line and a ground select line voltage applied to the ground select line from the power supply voltage, 
 a program voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate a program voltage applied to a select word line among the plurality of word lines during from the power supply voltage a program operation; and 
 a pass voltage generator configured to receive the power supply voltage via the power supply lines from the external device and generate a pass voltage applied to the plurality of word lines from the power supply voltage during the program operation, 
   wherein the program voltage and the pass voltage are high voltages higher than the power supply voltage.