FinFET device with epitaxial structure

Abstract

A FinFET device includes a substrate, a fin, and isolation regions on either side of the fin. The device also includes sidewall spacers above the isolation regions and formed along the fin structure. A recessing trench is formed by the sidewall spacers and the fin, and an epitaxially-grown semiconductor material is formed in and above the recessing trench, forming an epitaxial structure.

What is claimed is: 
     
       1. A method comprising:
 forming a first fin and a second fin separated by a distance S on a semiconductor substrate, wherein the first fin is directly adjacent to the second fin; 
 forming a gate structure over a first portion of the first fin and a first portion of the second fin;  
 forming a dielectric isolation feature on the semiconductor substrate, the dielectric isolation feature having a first height; 
 forming aperforming a process that forms first sidewall spacerspacers over the dielectric isolation feature along a sidewallsidewalls of the first fin and second sidewall spacers over the dielectric isolation feature along sidewalls of the second fin, the first sidewall spacerspacers and the second sidewall spacers each having a secondfirst height defined between a top surface of the dielectric isolation feature and top surfaces respectively of the first sidewall spacers and the second sidewall spacers; 
 removingrecessing a second portion of the first fin and a second portion of the second fin, such that a remaining second portion of the first finhas a third height, wherein, the first sidewall spacerspacers, and the first findielectric isolation feature define a first trench and a remaining second portion of the second fin, the second sidewall spacers, and the dielectric isolation feature define a second trench; 
 forming a first source/drain featureepitaxially growing a material in the first trench over the remaining second portion of the first fin to form a first source/drain feature and in the second trench over the remaining second portion of the second fin to form a second source/drain feature, wherein each of the first source/drain feature and the second source/drain feature has a fourthtop portion over a bottom portion, the top portion having a greater width than the bottom portion, and each of the top portion of the first source/drain feature and the second source/drain feature has a second height,; and 
 wherein the fourth height is greater than the second height and the first height is greater than the third height second height is inversely proportional to the first height and the first height is adjusted during the process that forms the first sidewall spacers and the second sidewall spacers to tune the second height. 
 
     
     
       2. The method of  claim 1 , wherein forming the first source/drain feature in the trench over the remaining portion of the first fin includes forming the first source/drain feature directly on the remaining portion of the first fin such that the first source/drain feature physically contacts the remaining portion of the first fin a merging distance is defined between a vertex of the first source/drain feature and a vertex of the second source/drain feature, the merging distance is proportional to the first height, and the first height is adjusted during the process that forms the first sidewall spacers and the second sidewall spacers to tune the merging distance. 
     
     
       3. The method of  claim 1 , wherein forming the first source/drain feature in the trench over the remaining portion of the first fin includes forming an epitaxial material on the remaining portion of the first fin and the second source/drain feature each has a width defined as a greatest distance between two vertexes respectively of the first source/drain feature and the second source/drain feature, the width is inversely proportional to the first height, and the first height is adjusted during the process that forms the first sidewall spacers and the second sidewall spacers to tune the width. 
     
     
       4. The method of  claim 1 , further comprising  wherein forming the gate structure over the portion of the first fin and the second fin comprises: forming a gate dielectric layer over the portion of the first fin; and the portion of the second fin; and forming a gate electrode over the gate dielectric layer. 
     
     
       5. The method of  claim 1 , wherein the gate dielectric layer includes a high-k dielectric material and wherein the gate electrode includes a metal material performing the process that forms the first sidewall spacers over the dielectric isolation feature along the sidewalls of the first fin and the second sidewall spacers over the dielectric isolation feature along the sidewalls of the second fin includes:
 depositing a dielectric material over the gate structure, the first fin, and the second fin; and 
 etching back the dielectric material, wherein the etching back is controlled so the first height is a pre-determined spacer height, wherein the pre-determined spacer height achieves target dimensions for the first source/drain feature and the second source/drain feature. 
 
     
     
       6. The method of claim  1  5, wherein the remaining portion of first fin has a first width and wherein the first source/drain feature has a second width that is greater than the first width etching back is controlled by adjusting etching parameters of over etch. 
     
     
       7. The method of claim  1  5, wherein the remaining portion of the first fin has a first width and wherein the first source/drain feature has a first portion having the first width and a second portion having a second width that is greater than the first width etching back includes anisotropically etching the dielectric material. 
     
     
       8. The method of  claim 1 , wherein, forming the first fin on the semiconductor substrate includes forming a second fin adjacent the first fin on the semiconductor substrate,
 wherein removing the portion of the first fin includes removing a portion of the second fin such that a remaining portion of the second fin has the third height, and 
 wherein forming the first source/drain feature in the trench over the remaining portion of the first fin includes forming a second source/drain feature on the remaining portion of the second fin the performing the process that forms the first sidewall spacers over the dielectric isolation feature along the sidewalls of the first fin and the second sidewall spacers over the dielectric isolation feature along the sidewalls of the second fin further forms gate spacers along sidewalls of a gate stack of the gate structure. 
 
     
     
       9. The method of claim  8  1, wherein the first and second source/drain features do not physically contact one another source/drain feature physically contacts the second source/drain feature, wherein the first height is adjusted during the process that forms the first sidewall spacers and the second sidewall spacers to achieve a target distance between the first source/drain feature and the second source/drain feature. 
     
     
       10. The method of claim  8  1, wherein the first and second source/drain features are merged together such that the first and second/source drain features physically contact one another source/drain feature and the second source/drain feature are merged together, such that the first source/drain feature physically contacts the second/source drain feature, wherein the first height is adjusted during the process that forms the first sidewall spacers and the second sidewall spacers to achieve a target merging between the first source/drain feature and the second source/drain feature. 
     
     
       11. A device comprising:
 a first fin formed on and a second fin separated by a distance S disposed over a semiconductor substrate, wherein the first fin is directly adjacent to the second fin, each of the first fin and the second fin has a first width, and each of the first fin and the second fin has a total fin height between a top surface of the semiconductor substrate and a bottom surface of a gate structure; 
 a first sidewall spacer having a first height and disposed along a sidewall of the first fin, wherein the first sidewall spacer and the first fin define a trench; and 
 a first source/drain feature disposed over a recessed portion of the first fin within the trench and a second source/drain feature disposed over a recessed portion of the second fin, wherein each of the recessed portion of the first fin and the recessed portion of the second fin has a recessed fin height between the top surface of the semiconductor substrate and a bottom surface of first source/drain feature and a bottom surface of the second source/drain feature, respectively, and the recessed fin height is less than the total fin height, and further wherein each of the first source/drain feature having and the second source/drain feature has a first portion that has the first width and a second portion disposed over the first portion that has a second width that is greater than the first width, wherein the first source/drain feature has a second height that that is greater than the first height; 
 a dielectric isolation feature disposed over the top surface of the semiconductor substrate, wherein the dielectric isolation feature has a thickness between the top surface of the semiconductor substrate and a top surface of the dielectric isolation feature and the thickness is less than the total fin height and greater than the recessed fin height, such that the dielectric isolation feature entirely covers sidewalls of the recessed portion of the first fin and sidewalls of the recessed portion of the second fin and partially covers sidewalls of the first portion of the first source/drain feature and sidewalls of the first portion of the second source/drain feature; 
 first sidewall spacers disposed over the dielectric isolation feature and partially covering the sidewalls of the first portion of the first source/drain feature, wherein the first sidewall spacers do not physically contact the second portion of the first source/drain feature; 
 second sidewall spacers disposed over the dielectric isolation feature and partially covering the sidewalls of the first portion of the second source/drain feature, wherein the second sidewall spacers do not physically contact the second portion of the second source/drain feature; 
 wherein each of the first sidewall spacers and the second sidewall spacers has a fin spacer height between a top surface of the dielectric isolation feature and top surfaces respectively of the first sidewall spacers and the second sidewall spacers; 
 wherein the fin spacer height is equal to a total fin spacer height of fin sidewall spacers along the first source/drain feature and the second source/drain feature; 
 wherein a sum of the thickness of the dielectric isolation feature and the total fin spacer height is less than the total fin height; 
 wherein the second portion of each of the first source/drain feature and the second source/drain feature do not physically contact the dielectric isolation feature; 
 wherein the second portion of each of the first source/drain feature and the second source/drain feature has a source/drain height between bottom surfaces respectively of the second portions of the first source/drain feature and the second source/drain feature and top surfaces respectively of the second portions of the first source/drain feature and the second source/drain feature; and 
 wherein the source/drain height is inversely proportional to the total fin spacer height, such that the source/drain height increases as the total fin spacer height decreases and the source/drain height decreases as the total fin spacer height increases. 
 
     
     
       12. The device of  claim 11 , wherein the second portion of the first fin includes source/drain feature and the second portion of the second source/drain feature each include a first facet that is parallel to a second facet and a third facet that is parallel to the a fourth facet. 
     
     
       13. The device of  claim 11 , further comprising a gate structure disposed over the first fin, wherein the gate structure includes a metal gate electrode disposed over a high-k dielectric layer. 
     
     
       14. The device of  claim 11 , wherein the first portion of the first fin includes a sidewall surface having a first segment that is covered by the first sidewall spacer and a second segment that is free of the first sidewall spacer second portion of the first source/drain feature and the second portion of the second source/drain feature each has a width defined as a greatest distance between two vertexes respectively of the second portion of the first source/drain feature and the second portion of the second source/drain feature and the width is inversely proportional to the fin spacer height. 
     
     
       15. The device of  claim 11 , further comprising:
 a second fin formed on the semiconductor substrate; 
 a dielectric isolation structure disposed on the semiconductor substrate and extending from the first fin to the second fin; 
 a second source/drain feature disposed over the second fin, the second source/drain feature having a first portion that has the first width and a second portion that has the second width that is greater than the first width, wherein the second source/drain feature has the second height; and 
 a second sidewall spacer disposed along a sidewall of the second fin, the second sidewall spacer having the first height wherein a merging distance is defined between a vertex of the second portion of the first source/drain feature and a vertex of the second portion of the second source/drain feature and the merging distance is proportional to the fin spacer height. 
 
     
     
       16. A device comprising:
 a dielectric isolation feature disposed on a semiconductor substrate; 
 a first fin and a second fin separated by a distance S formed on the semiconductor substrate and at least partially surrounded by the dielectric isolation feature, the first fin and the second fin having a first width measured between opposing sidewalls of the dielectric isolation feature and the first fin and the second fin having a total fin height between a top surface of the semiconductor substrate and a bottom surface of a gate structure, wherein a portion of the first fin and a portion of the second fin have a top surface that is lower than a top surface of the dielectric isolation feature and the portion of the first fin and the portion of the second fin have a recessed fin height that is less than the total fin height; 
 a first source/drain feature disposed directly on the top surface of the portion of the first fin and a second source/drain feature disposed directly on the top surface of the portion of the second fin, wherein the first source/drain feature having and the second source/drain feature each has a first portion at least partially surrounded by the dielectric isolation feature and having the first width measured between opposing sidewalls of the dielectric isolation feature, and further wherein the first source/drain feature having and the second source/drain feature each has a second portion interfacing with above the first portion and having a second width that is greater than the first width, wherein a merging distance is defined between the second portion of the first source/drain feature has a first height and the second portion of the second source/drain feature; and 
 a spacer first fin spacers disposed directly on the top surface of the dielectric isolation feature and at least partially along a sidewall sidewalls of the first portion of the first source/drain feature and second fin spacers disposed directly on the top surface of the dielectric isolation feature and at least partially along sidewalls of the first portion of the second source/drain feature, wherein: 
 the spacer first fin spacers and the second fin spacers each having a second fin spacer height that is between the top surface of the dielectric isolation feature and top surfaces respectively of the first fin spacers and the second fin spacers, 
 the fin spacer height is equal to a total fin spacer height of fin sidewall spacers along the first source/drain feature and the second source/drain feature, 
 the first fin spacers do not physically contact the second portion of the first source/drain feature and the second fin spacers do not physically contact the second portion of the second source/drain feature, 
 a sum of a thickness of the dielectric isolation feature and the total fin spacer height is less than the total fin height, 
 the second portion of each of the first source/drain feature and the second source/drain feature do not physically contact the dielectric isolation feature, and 
 less thanthe merging distance is proportional to the firstfin spacer height, such that the merging distance decreases as the fin spacer height decreases and the merging distance increases as the fin spacer height increases. 
 
     
     
       17. The device of  claim 16 , wherein the dielectric isolation feature has a third height that is greater than a fourth height of the fin merging distance equals zero. 
     
     
       18. The device of  claim 16 , further comprising a the gate structure having a metal layer and a high-k dielectric layer. 
     
     
       19. The device of  claim 16 , wherein each of the first portion of the first source/drain feature and the first portion of the second source/drain feature has a sidewall that includes a first segment that is covered by the dielectric isolation feature, a second segment that is covered respectively by the spacer first fin spacers and the second fin spacers, and a third segment that is not covered by the dielectric isolation feature and the spacer first fin spacers and the second fin spacers, respectively. 
     
     
       20. The device of  claim 16 , wherein the source/drain feature is merged with another source/drain feature merging distance is a negative number. 
     
     
       21. The method of claim 1, wherein the epitaxially growing the material includes epitaxially growing silicon. 
     
     
       22. The method of claim 1, wherein the recessing the second portion of the first fin and the second portion of the second fin includes etching the second portion of the first fin and the second portion of the second fin until a top surface of the second portion of the first fin and a top surface of the second portion of the second fin is lower than a top surface of the dielectric isolation feature. 
     
     
       23. The method of claim 1, wherein the epitaxially growing the material includes epitaxially growing silicon germanium. 
     
     
       24. The method of claim 1, wherein the bottom portion of each of the first source/drain feature and the second source/drain feature has a third height, wherein the third height is greater than the first height. 
     
     
       25. The device of claim 11, wherein the dielectric isolation feature is disposed between the first fin and the second fin. 
     
     
       26. The device of claim 11, wherein the first fin and the second fin include a first semiconductor material, the first source/drain feature and the second source/drain feature include a second semiconductor material, the dielectric isolation feature includes a first dielectric material, and the first sidewall spacers and the second sidewall spacers include a second dielectric material. 
     
     
       27. The device of claim 11, wherein:
 the first portion of the first source/drain feature has a first interface with the second portion of the first source/drain feature and the first portion of the second source/drain feature has a second interface with the second portion of the second source/drain feature; and   a distance between the top surface of the dielectric isolation feature and the first interface and the second interface, respectively, is greater than the total fin spacer height.   
     
     
       28. The device of claim 11, wherein the second portion of the first source/drain feature and the second portion of the second source/drain feature each have rhombus-shaped cross-sectional profiles. 
     
     
       29. The device of claim 16, wherein the merging distance is a positive number. 
     
     
       30. The device of claim 16, wherein:
 the first portion of the first source/drain feature is connected to the second portion of the first source/drain feature at a first interface;   the second portion of the first source/drain feature is connected to the second portion of the second source/drain feature at a second interface;   the second portion of the first source/drain feature has a first height between the first interface and a topmost point of the second portion of the first source/drain feature, wherein the first height is inversely proportional to the fin spacer height; and   the second portion of the second source/drain feature has a second height between the second interface and a topmost point of the second portion of the second source/drain feature, wherein the second height is inversely proportional to the fin spacer height.   
     
     
       31. The device of claim 16, wherein:
 the second portion of the first source/drain feature is diamond-shaped and has a first width defined between vertexes of the first source/drain feature, wherein the first width is inversely proportional to the fin spacer height; and   the second portion of the second source/drain feature is diamond-shaped and has a second width defined between vertexes of the first source/drain feature, wherein the second width is inversely proportional to the fin spacer height.