Semiconductor device and method of fabricating the same

Abstract

A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a gate dielectric pattern disposed on a substrate; 
 a lower gate electrode disposed on the gate dielectric pattern, the lower gate electrode including a bottom portion parallel to the substrate and sidewall portions extending in a vertical direction from both ends of the bottom portion; and 
 an upper gate electrode disposed on the bottom portion and sidewall portions of the lower gate electrode, the upper gate electrode having a lower resistivity than the lower gate electrode, 
 wherein the upper gate electrode is partially surrounded by the sidewall portions of the lower gate electrode, and 
 wherein a width of upper portions of the sidewall portions of the lower gate electrode is narrower than a width of lower portions of the sidewall portions of the lower gate electrode. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the lower gate electrode is formed by a sub-etching process. 
     
     
       3. The semiconductor device of  claim 1 , wherein the gate dielectric layer pattern includes an insulating pattern and a metal compound pattern. 
     
     
       4. The semiconductor device of  claim 3 , wherein the insulating pattern includes one of at least a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. 
     
     
       5. The semiconductor device of  claim 3 , wherein the metal compound pattern includes one of at least a metal oxide layer, a metal silicide layer, a metal nitride layer, and a metal oxynitride layer. 
     
     
       6. The semiconductor device of claim 1, further comprising spacers covering a sidewall of the lower gate electrode and a sidewall of the upper gate electrode. 
     
     
       7. A semiconductor device comprising:
 a gate dielectric pattern disposed on a substrate;   a lower gate electrode disposed on the gate dielectric pattern, the lower gate electrode including a bottom portion parallel to the substrate and sidewall portions extending in a vertical direction from both ends of the bottom portion; and   an upper gate electrode disposed on the bottom portion and sidewall portions of the lower gate electrode, the upper gate electrode having a lower resistivity than the lower gate electrode,   wherein the upper gate electrode is partially surrounded by the sidewall portions of the lower gate electrode,   wherein a width of upper portions of the sidewall portions of the lower gate electrode is narrower than a width of lower portions of the sidewall portions of the lower gate electrode, and   wherein the lower gate electrode includes a metal-containing layer.   
     
     
       8. The semiconductor device of claim 7, wherein the lower gate electrode includes at least one of a titanium nitride layer, a titanium silicide layer, a titanium aluminum nitride layer, a tantalum nitride layer, a titanium tantalum nitride layer, a tantalum aluminum nitride layer, or a tantalum silicide nitride layer. 
     
     
       9. The semiconductor device of claim 7, wherein the lower gate electrode includes a titanium nitride layer. 
     
     
       10. The semiconductor device of claim 7, wherein the upper gate electrode includes at least one of aluminum, aluminum alloy, tungsten, and copper. 
     
     
       11. The semiconductor device of claim 7, wherein a work function of the lower gate electrode and a work function of the upper gate electrode are different from each other. 
     
     
       12. The semiconductor device of claim 7, further comprising:
 spacers covering the sidewall portions of the lower gate electrode.   
     
     
       13. The semiconductor device of claim 7, further comprising:
 source and drain regions in the substrate on both sides of the lower gate electrode.   
     
     
       14. The semiconductor device of claim 7, further comprising:
 a metal compound pattern between the gate dielectric pattern and the lower gate electrode.   
     
     
       15. The semiconductor device of claim 14, wherein the metal compound pattern includes one of at least a metal oxide layer, a metal silicide layer, a metal nitride layer, and a metal oxynitride layer. 
     
     
       16. The semiconductor device of claim 7, wherein the gate dielectric pattern includes one of at least a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. 
     
     
       17. The semiconductor device of claim 7, further comprising:
 an interlayer dielectric on the substrate, and   wherein the sidewall portions of the lower gate electrode have top surfaces lower than a top surface of the interlayer dielectric.   
     
     
       18. The semiconductor device of claim 17, wherein the top surface of the interlayer dielectric is coplanar with a top surface of the upper gate electrode. 
     
     
       19. The semiconductor device of claim 18, wherein the upper gate electrode includes tungsten. 
     
     
       20. The semiconductor device of claim 18, further comprising:
 a metal compound pattern between the gate dielectric pattern and the lower gate electrode.   
     
     
       21. A semiconductor device comprising:
 a gate dielectric pattern disposed on a substrate;   a lower metal gate electrode disposed on the gate dielectric pattern, the lower metal gate electrode including a bottom portion parallel to the substrate and sidewall portions extending in a vertical direction from both ends of the bottom portion; and   an upper gate electrode disposed on the bottom portion and sidewall portions of the lower metal gate electrode, the upper gate electrode having a lower resistivity than the lower metal gate electrode,   wherein the upper gate electrode is partially surrounded by the sidewall portions of the lower metal gate electrode, and   wherein a width of upper portions of the sidewall portions of the lower metal gate electrode is narrower than a width of lower portions of the sidewall portions of the lower metal gate electrode.   
     
     
       22. The semiconductor device of claim 21, wherein the lower metal gate electrode includes at least one of a titanium nitride layer, a titanium silicide layer, a titanium aluminum nitride layer, a tantalum nitride layer, a titanium tantalum nitride layer, a tantalum aluminum nitride layer, or a tantalum silicide nitride layer. 
     
     
       23. The semiconductor device of claim 21, wherein the upper gate electrode includes at least one of aluminum, aluminum alloy, tungsten, and copper. 
     
     
       24. The semiconductor device of claim 21, further comprising:
 a metal compound pattern between the gate dielectric pattern and the lower metal gate electrode.   
     
     
       25. A semiconductor device comprising:
 a gate dielectric pattern disposed on a substrate;   a lower gate electrode disposed on the gate dielectric pattern, the lower gate electrode including a bottom portion parallel to the substrate and sidewall portions extending in a vertical direction from both ends of the bottom portion; and   an upper gate electrode disposed on the bottom portion and sidewall portions of the lower gate electrode, the upper gate electrode having a lower resistivity than the lower gate electrode,   wherein the upper gate electrode is partially surrounded by the sidewall portions of the lower gate electrode,   wherein a width of upper portions of the sidewall portions of the lower gate electrode is narrower than a width of lower portions of the sidewall portions of the lower gate electrode, and   wherein the lower gate electrode comprise a titanium nitride layer.