USRE49820EActiveUtility

Semiconductor device having a self-forming barrier layer at via bottom

62
Assignee: GLOBALFOUNDRIES INCPriority: Oct 10, 2012Filed: Aug 31, 2019Granted: Jan 30, 2024
Est. expiryOct 10, 2032(~6.3 yrs left)· nominal 20-yr term from priority
Inventors:Larry ZhaoMing HeXunyuan ZhangSean Xuan Lin
H10W 20/425H10W 20/076H10W 20/047H10W 20/47H10W 20/035H10W 20/0552H10W 20/42H01L 23/5226H01L 21/76831H01L 21/76846H01L 21/76855H01L 23/53238H01L 23/53295H01L 2924/0002H01L 2924/00
62
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Cited by
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References
39
Claims

Abstract

An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for forming a barrier layer in a semiconductor device, comprising:
 selectively applying the barrier layer along a bottom surface of a via of the semiconductor device, the barrier layer formed along a metal layer of the semiconductor device;   applying a liner layer along a set of sidewalls of the via; and   annealing the semiconductor device.   
     
     
       2. The method of  claim 1 , the barrier layer comprising a metal capable of copper (Cu) diffusion. 
     
     
       3. The method of  claim 1 , the liner layer further being applied over the barrier layer and the liner layer comprising a metal. 
     
     
       4. The method of  claim 1 , the barrier layer being applied via a process selected from a group consisting of: chemical vapor deposition (CVD), physical vapor deposition (PVD), gas cluster ion beam (GCIB) infusion, and electroless deposition (ELD). 
     
     
       5. The method of  claim 1 , further comprising applying a seed layer over the barrier layer. 
     
     
       6. The method of  claim 1 , the via being formed through an ultra low k (ULK) layer and a cap layer of the semiconductor device, the ultra low k layer being formed over the cap layer. 
     
     
       7. A method for forming a barrier layer in a semiconductor device, comprising:
 selectively applying the barrier layer along a bottom surface of a via of the semiconductor device, the via being formed through an ultra low k layer and a cap layer of the semiconductor device;   applying a liner layer over the barrier layer and along a set of sidewalls of the via;   filling the via with a metal; and   processing the semiconductor device to remove the liner layer from over the barrier layer.   
     
     
       8. The method of  claim 7 , the barrier layer comprising a metal capable of copper (Cu) diffusion. 
     
     
       9. The method of  claim 1 , the liner layer further being applied over the barrier layer and the liner layer comprising a metal. 
     
     
       10. The method of  claim 7 , the barrier layer being applied via a process selected from a group consisting of: chemical vapor deposition (CVD), physical vapor deposition (PVD), gas cluster ion beam (GCIB) infusion, and electroless deposition (ELD). 
     
     
       11. The method of  claim 7 , further comprising applying a seed layer over the barrier layer. 
     
     
       12. The method of  claim 7 , the via being formed through an ultra low k (ULK) layer and a cap layer of the semiconductor device, the ultra low k layer being formed over the cap layer. 
     
     
       13. The method of  claim 12 , the barrier layer forming a barrier between the via and a metal layer of the semiconductor device, the cap layer being formed over the metal layer. 
     
     
       14. A semiconductor device, comprising:
 a first metal layer;   a cap formed over the first metal layer;   an ultra low k layer formed over the cap layer; and   a via formed through the ultra low k layer and the cap layer, the via comprising a barrier layer selectively formed along a bottom surface of the via, and a liner layer along a set of sidewall of the via.   
     
     
       15. The semiconductor surface of  claim 14 , further comprising a second metal layer formed inside of the via. 
     
     
       16. The semiconductor surface of  claim 14 , the liner layer comprising a metal selected from a group consisting of manganese (Mn) and aluminum (Al). 
     
     
       17. The semiconductor surface of  claim 14 , the second metal layer comprising copper (Cu). 
     
     
       18. The semiconductor surface of  claim 14 , the barrier layer comprising a metal selected from the group consisting of: cobalt (Co), tantalum (Ta), and copper-tungsten phosphide (CoWP). 
     
     
       19. The semiconductor surface of  claim 14 , further comprising a seed layer applied in the via over the liner layer and the barrier layer. 
     
     
       20. A method of forming a semiconductor device, the method comprising:
 forming a dielectric layer over a first metal layer;   forming a via extending through the dielectric layer;   applying a barrier layer only along a bottom surface of the via on the first metal layer;   applying a liner layer along a plurality of sidewalls of the via; and   filling the via with a second metal layer.    
     
     
       21. The method of claim 20, wherein the barrier layer comprises ruthenium (Ru).  
     
     
       22. The method of claim 20, wherein the liner layer is further applied over the barrier layer, and the liner layer comprises a metal.  
     
     
       23. The method of claim 21, wherein the barrier layer is applied via a process selected from the group consisting of: chemical vapor deposition (CVD), physical vapor deposition (PVD), gas cluster ion beam (GCIB) infusion, and electroless deposition (ELD).  
     
     
       24. The method of claim 20, further comprising:
 applying a seed layer over the barrier layer.    
     
     
       25. The method of claim 20, wherein the via is formed through a cap layer, and the dielectric layer is formed over the cap layer.  
     
     
       26. The method of claim 20, wherein the second metal layer comprises copper (Cu).  
     
     
       27. A method of forming a semiconductor device, the method comprising:
 forming a cap layer and a dielectric layer over a metal layer;   forming a via extending through the cap layer and the dielectric layer;   selectively applying a barrier layer only along a bottom surface of the via on the metal layer;   applying a liner layer over the barrier layer and along a plurality of sidewalls of the via; and   filling the via with copper (Cu).    
     
     
       28. The method of claim 27, wherein the barrier layer comprises a metal capable of acting as a copper (Cu) diffusion barrier.  
     
     
       29. The method of claim 27, wherein the barrier layer comprises ruthenium (Ru).  
     
     
       30. The method of claim 27, wherein the barrier layer is applied via a process selected from the group consisting of: chemical vapor deposition (CVD), physical vapor deposition (PVD), gas cluster ion beam (GCIB) infusion, and electroless deposition (ELD).  
     
     
       31. The method of claim 27, further comprising:
 applying a seed layer over the barrier layer.    
     
     
       32. The method of claim 27, wherein the dielectric layer is formed over the cap layer.  
     
     
       33. The method of claim 32, wherein the barrier layer forms a barrier between the via and the metal layer.  
     
     
       34. A semiconductor device comprising:
 a first metal layer;   a cap layer over the first metal layer;   a dielectric layer over the cap layer;   a via extending through the dielectric layer and the cap layer to the first metal layer;   a barrier layer on only the first metal layer along a bottom surface of the via; and   a liner layer along a plurality of sidewalls of the via and over a top surface of the barrier layer.    
     
     
       35. The semiconductor device of claim 34, further comprising:
 a second metal layer inside the via.    
     
     
       36. The semiconductor device of claim 34, wherein the liner layer comprises manganese (Mn) or aluminum (Al).  
     
     
       37. The semiconductor device of claim 35, wherein the second metal layer comprises copper (Cu).  
     
     
       38. The semiconductor device of claim 34, wherein the barrier layer comprises ruthenium (Ru).  
     
     
       39. The semiconductor device of claim 34, further comprising:
 a seed layer in the via over the liner layer and the barrier layer.

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