Inventor · disambiguated record
Ming He
Also filed as: HE MING · HE MING-XIANG
23 granted patents·18 pending applications·129 citations·filing 2007–2025
94Inventor score
Files withGLOBALFOUNDRIES INC20SAMSUNG ELECTRONICS CO LTD16LIN SEAN X2COMPAL ELECTRONICS INC1TANWAR KUNALJEET1
Top patents by PatentIndex Score
41 records- 0195US8586473B1Methods for fabricating integrated circuits with ruthenium-lined copperTANWAR KUNALJEET·Filed 2012·Granted Nov 19, 2013·45 cites·20 claims
- 0292US12356665B2Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methodsSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Jul 8, 2025·2 cites·18 claims
- 0392US9431294B2Methods of producing integrated circuits with an air gapGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 30, 2016·14 cites·19 claims
- 0490US9318437B1Moisture scavenging layer for thinner barrier application in beol integrationGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 19, 2016·9 cites·20 claims
- 0589US8753975B1Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 17, 2014·10 cites·21 claims
- 0689US8517769B1Methods of forming copper-based conductive structures on an integrated circuit deviceLIN SEAN X·Filed 2012·Granted Aug 27, 2013·14 cites·41 claims
- 0787US8907483B2Semiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2012·Granted Dec 9, 2014·7 cites·19 claims
- 0884US9691971B2Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 27, 2017·5 cites·18 claims
- 0983US10199270B2Multi-directional self-aligned multiple patterningGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 5, 2019·5 cites·20 claims
- 1082US8932934B2Methods of self-forming barrier integration with pore stuffed ULK materialGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 13, 2015·6 cites·13 claims
- 1177US9087881B2Electroless fill of trench in semiconductor structureGLOBALFOUNDRIES INC·Filed 2013·Granted Jul 21, 2015·4 cites·12 claims
- 1276US9054052B2Methods for integration of pore stuffing materialGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 9, 2015·3 cites·17 claims
- 1374US2025311304A1Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methodsSAMSUNG ELECTRONICS CO LTD·Filed 2025·Application pending·0 cites
- 1471US10510675B2Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident lightGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 17, 2019·2 cites·7 claims
- 1567US12456647B2Nanosheet transistor devices and related fabrication methodsSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Oct 28, 2025·0 cites·16 claims
- 1667US2023317513A1Fully aligned via integration with selective catalyzed vapor phase grown materialsSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 1766US11705363B2Fully aligned via integration with selective catalyzed vapor phase grown materialsSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Jul 18, 2023·0 cites·16 claims
- 1864US8859419B2Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting deviceGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 14, 2014·1 cites·15 claims
- 1964US8673766B2Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper depositionLIN SEAN X·Filed 2012·Granted Mar 18, 2014·2 cites·18 claims
- 2062USRE49820ESemiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2019·Granted Jan 30, 2024·0 cites·39 claims
- 2158US2023178440A1Methods of forming integrated circuit devices including stacked transistors and integrated circuit devices formed by the sameSAMSUNG ELECTRONICS CO LTD·Filed 2022·Application pending·0 cites
- 2257US11978668B2Integrated circuit devices including a via and methods of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted May 7, 2024·0 cites·17 claims
- 2356US9318436B2Copper based nitride liner passivation layers for conductive copper structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 19, 2016·0 cites·10 claims
- 2455USRE47630ESemiconductor device having a self-forming barrier layer at via bottomGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 1, 2019·0 cites·19 claims
- 2555US2024429307A1Systems and methods of applying stress in transistorsSAMSUNG ELECTRONICS CO LTD·Filed 2024·Application pending·0 cites
- 2653US2024405128A1Field effect transistor (fet) and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2024·Application pending·0 cites
- 2752US2025072098A1Source/drain isolation of top and bottom tiers of 3d field-effect transistorsSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 2852US2024347537A1Common output in 3d stack fetSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 2952US2025366107A1System and methods for shaped epitaxial stressorsSAMSUNG ELECTRONICS CO LTD·Filed 2025·Application pending·0 cites
- 3052US2024413232A1High performance fetsSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 3150US2024047539A13d stacked field-effect transistor device with pn junction structureSAMSUNG ELECTRONICS CO LTD·Filed 2022·Application pending·0 cites
- 3250US2024047456A13dsfet standard cell architecture with source-drain junction isolationSAMSUNG ELECTRONICS CO LTD·Filed 2022·Application pending·0 cites
- 3347US2025359192A1System and method for high stress transfer to channelSAMSUNG ELECTRONICS CO LTD·Filed 2025·Application pending·0 cites
- 3444US9165770B2Methods for fabricating integrated circuits using improved masksGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 20, 2015·0 cites·14 claims
- 3543US2015228585A1Self-forming barrier integrated with self-aligned capGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 3642US2014145332A1Methods of forming graphene liners and/or cap layers on copper-based conductive structuresGLOBALFOUNDRIES INC·Filed 2012·Application pending·0 cites
- 3742US2014353805A1Methods of semiconductor contaminant removal using supercritical fluidGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 3841US2008149370A1Local temperature control fixture applied to reflow process for circuit boardCOMPAL ELECTRONICS INC·Filed 2007·Application pending·0 cites
- 3939US2014057435A1Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit deviceZHANG XUNYUAN·Filed 2012·Application pending·0 cites
- 4035US9576852B2Integrated circuits with self aligned contacts and methods of manufacturing the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·0 cites·20 claims
- 4134US2017154816A1Amorphous metal interconnections by subtractive etchGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →