Integrated circuit devices

Abstract

An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

What is claimed is: 
     
       1. A fabricating method of an integrated circuit device, the method comprising:
 providing a substrate having a first region and a second region defined therein;   forming a first fin in the first region and forming a second fin in the second region;   forming a first gate electrode intersecting the first fin in the first region and forming a second gate electrode intersecting the second fin in the second region;   forming a first recess in the first fin at either side of the first gate electrode in the first region and forming a second recess in the second fin at either side of the second gate electrode in the second region;   forming a first source/drain in the first recess; and   forming a second source/drain in the second recess,   wherein a depth of the first recess is different from a depth of the second recess, and wherein   an impurity concentration of the first source/drain is different from an impurity concentration of the second source/drain.   
     
     
       2. The method as claimed in  claim 1 , wherein the first source/drain has a first thickness in the first recess and the second source/drain has a second thickness in the second recess. 
     
     
       3. The method as claimed in  claim 2 , wherein the first thickness of the first source/drain is different from the second thickness of the second source/drain. 
     
     
       4. The method as claimed in  claim 1 , wherein the forming the first source/drain and the second source/drain comprises using an epitaxial process, and impurities of the first source/drain and the second source/drain is in-situ doped during the epitaxial process. 
     
     
       5. The method as claimed in  claim 1 , wherein the forming the first fin and the second fin comprises:
 forming a mask pattern on the substrate, and   etching the substrate using the mask pattern as an etch mask.   
     
     
       6. An integrated circuit device comprising:
 a substrate including a first region and a second region;   a first nanowire shaped transistor disposed on the first region of the substrate, and including a first source/drain; and   a second nanowire shaped transistor disposed on the second region of the substrate, and including a second source/drain, wherein:   the first source/drain has a first thickness, and   the second source/drain has a second thickness that is different from the first thickness, lower surfaces of the first source/drain and the second source/drain being at different heights relative to a bottom of the substrate.    
     
     
       7. The integrated circuit device of claim 6, wherein the first region is a logic region, and the second region is an SRAM region.  
     
     
       8. The integrated circuit device of claim 6, wherein each of the first region and the second region is a logic region.  
     
     
       9. The integrated circuit device of claim 6, wherein the first nanowire shaped transistor is a pull-up transistor, and
 the second nanowire shaped transistor is a pull-down transistor or a pass transistor.    
     
     
       10. The integrated circuit device of claim 6, wherein the first nanowire shaped transistor includes K first nanowires that are stacked vertically one on another, K being an integer greater than one, and
 the second nanowire shaped transistor includes L second nanowires that are stacked vertically one on another, L being an integer greater than one.    
     
     
       11. The integrated circuit device of claim 10, wherein K is equal to L.  
     
     
       12. The integrated circuit device of claim 11, wherein the first source/drain is connected to M nanowires among the K first nanowires, M being a positive integer, and
 the second source/drain is connected to N nanowires among the L second nanowires, N being a positive integer.    
     
     
       13. The integrated circuit device of claim 12, wherein M is different from N.  
     
     
       14. The integrated circuit device of claim 10, wherein a cross-sectional shape of the K first nanowires and the L second nanowires is oval or rectangular.  
     
     
       15. The integrated circuit device of claim 6, wherein the first nanowire shaped transistor is a PMOS transistor.  
     
     
       16. The integrated circuit device of claim 6, wherein each of the first nanowire shaped transistor and the second nanowire shaped transistor is a PMOS transistor.  
     
     
       17. The integrated circuit device of claim 6, wherein each of the first nanowire shaped transistor and the second nanowire shaped transistor is an NMOS transistor.  
     
     
       18. The integrated circuit device of claim 6, wherein each of the first source/drain and the second source/drain includes SiGe, and
 each of a first channel of the first nanowire shaped transistor and a second channel of the second nanowire shaped transistor includes Si.    
     
     
       19. The integrated circuit device of claim 6, wherein each of the first source/drain and the second source/drain includes SiC, and
 each of a first channel of the first nanowire shaped transistor and a second channel of the second nanowire shaped transistor includes Si.    
     
     
       20. The integrated circuit device of claim 6, wherein each of the first source/drain and the second source/drain includes SiC or Si.  
     
     
       21. The integrated circuit device of claim 6, wherein each of the first source/drain and the second source/drain has a first lattice constant.  
     
     
       22. The integrated circuit device of claim 21, wherein each of a first channel of the first nanowire shaped transistor and a second channel of the second nanowire shaped transistor has a second lattice constant that is different from the first lattice constant.  
     
     
       23. The integrated circuit device of claim 6, further comprising:
 a first gate electrode disposed on the first region of the substrate; and   a second gate electrode disposed on the second region of the substrate,   wherein the first gate electrode includes a first metal laver and a second metal layer disposed on the first metal layer, and   the second gate electrode includes a third metal layer and a fourth metal layer disposed on the third metal layer.    
     
     
       24. The integrated circuit device of claim 23, wherein the first metal layer includes TiN, TaN, TiC or TaC, and
 the second metal layer includes W or Al.    
     
     
       25. The integrated circuit device of claim 23, wherein each of the first metal layer and the third metal layer is U-shaped.  
     
     
       26. The integrated circuit device of claim 23, wherein each of the first gate electrode and the second gate electrode is U-shaped.  
     
     
       27. The integrated circuit device of claim 6, further comprising:
 a first gate insulation layer disposed on the first region of the substrate; and   a second gate insulation layer disposed on the second region of the substrate,   wherein the first gate insulation layer includes a high-k material having a higher dielectric constant than silicon oxide.    
     
     
       28. The integrated circuit device of claim 27, wherein the first gate insulation layer includes HfO2, ZrO2 or Ta2O5.  
     
     
       29. An integrated circuit device comprising:
 a substrate including a first region and a second region;   a first transistor disposed on the first region of the substrate, and including a first source/drain and K nanowires, K being an integer greater than one; and   a second transistor disposed on the second region of the substrate, and including a second source/drain and K nanowires,   wherein the first source/drain has a first thickness,   the second source/drain has a second thickness that is different from the first thickness,   the first source/drain is directly contacting and electrically connected to M nanowires among the K nanowires of the first transistor, M being a positive integer, and   the second source/drain is directly contacting and electrically connected to N nanowires among the K nanowires of the second transistor, N being a positive integer different from M, a difference between M and N corresponding to a difference in thickness between the first source/drain and the second source/drain.    
     
     
       30. The integrated circuit device of claim 29, wherein the first region is a logic region, and the second region is an SRAM region.  
     
     
       31. The integrated circuit device of claim 29, wherein each of the first region and the second region is a logic region.  
     
     
       32. The integrated circuit device of claim 29, wherein the first transistor is a PMOS transistor.  
     
     
       33. The integrated circuit device of claim 29, wherein each of the first transistor and the second transistor is a PMOS transistor.  
     
     
       34. The integrated circuit device of claim 29, wherein each of the first transistor and the second transistor is an NMOS transistor.  
     
     
       35. An integrated circuit device comprising:
 a substrate including a first region and a second region;   a first fin-shaped transistor disposed on the first region of the substrate, and including a first source/drain and a first channel; and   a second fin-shaped transistor disposed on the second region of the substrate, and including a second source/drain and a second channel,   wherein the first source/drain has a first thickness,   the second source/drain has a second thickness that is different from the first thickness,   a lower surface of the first source/drain is disposed higher than an upper surface of the substrate,   a lower surface of the second source/drain is disposed higher than the upper surface of the substrate, the lower surfaces of the first source/drain and the second source/drain being at different heights relative to a bottom of the substrate, and   each of the first channel and the second channel includes Si.    
     
     
       36. The integrated circuit device of claim 35, wherein the first region is a logic region, and the second region is an SRAM region.  
     
     
       37. The integrated circuit device of claim 35, wherein the first fin-shaped transistor is a pull-up transistor, and
 the second fin-shaped transistor is a pull-down transistor or a pass transistor.    
     
     
       38. The integrated circuit device of claim 35 wherein the first fin-shaped transistor is a PMOS transistor.  
     
     
       39. The integrated circuit device of claim 35, wherein each of the first fin-shaped transistor and the second fin-shaped transistor is a PMOS transistor.  
     
     
       40. The integrated circuit device of claim 35, wherein a first stress applied by the first source/drain to a first channel of the first fin-shaped transistor is different from a second stress applied by the second source/drain to a second channel of the second fin-shaped transistor.  
     
     
       41. The integrated circuit device of claim 40, wherein the first channel and the second channel have a same second lattice constant that is different from a first lattice constant.  
     
     
       42. The integrated circuit device of claim 35, wherein the first source/drain includes a compressive stress material.  
     
     
       43. The integrated circuit device of claim 35, wherein the substrate is a silicon on insulator (SOI) substrate.  
     
     
       44. The integrated circuit device of claim 35, wherein the first fin-shaped transistor includes a first fin having a width of 20 nm or less.