Semiconductor memory device having insulation patterns and cell gate patterns

Abstract

Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 insulation patterns and cell gate patterns that are alternately stacked on a substrate; 
 an active pattern disposed on the substrate and extending upward along sidewalls of the insulation patterns and sidewalls of the cell gate patterns; 
 a charge storage layer interposed between the sidewall sidewalls of the cell gate pattern patterns and the active pattern; 
 a blocking insulation layer interposed between the sidewall sidewalls of the cell gate pattern patterns and the charge storage layer; 
 a tunnel insulation layer interposed between the charge storage layer and the active pattern; and 
 a conductive barrier interposed between the blocking insulation layer and the sidewall of one of the cell gate pattern patterns and containing nitrogen metal nitride. 
 
     
     
       2. The semiconductor memory device of  claim 1 , wherein the one of the cell gate pattern patterns contains metals, the conductive barrier contains metal nitrides, and the one of the cell gate pattern patterns and the conductive barrier contain the same metals. 
     
     
       3. The semiconductor memory device of  claim 1 , wherein a part of at least the one of the cell gate pattern patterns coming in contact with the conductive barrier contains Group 4A element-metal compounds, the conductive barrier contains Group 4A element-metal nitrides, and the Group 4A element-metal compounds and the conductive barrier contain the same Group 4A elements and the same metals. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the conductive barrier is recessed sideward as compared to the sidewalls of the insulation patterns to define undercut regions, the charge storage layer comprises a plurality of charge storage layers that are disposed in the undercut regions, respectively, and the charge storage layers disposed in adjacent undercut regions are isolated from each other. 
     
     
       5. The semiconductor memory device of  claim 4 , wherein the tunnel insulation layer extends into successive undercut regions to be disposed between the charge storage layers that are isolated from each other and the active pattern. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein the active pattern is disposed in a hole penetrating successively through the insulation patterns and the cell gate patterns, and the cell gate patterns are a form of planar surface. 
     
     
       7. The semiconductor memory device of  claim 1 , wherein the cell gate patterns form lines extending along one direction in parallel with an upper surface of the substrate. 
     
     
       8. A semiconductor memory device comprising:
 insulation patterns and cell gate patterns that are alternately stacked on a substrate;   an active pattern disposed on the substrate and extending upward along sidewalls of the insulation patterns and sidewalls of the cell gate patterns;   a charge storage layer interposed between the sidewalls of the cell gate patterns and the active pattern;   a blocking insulation layer interposed between the sidewalls of the cell gate patterns and the charge storage layer;   a tunnel insulation layer interposed between the charge storage layer and the active pattern; and   a conductive barrier interposed between the blocking insulation layer and the sidewall of one of the cell gate patterns and containing nitrogen,   wherein the blocking insulation layer includes a plurality of layers, and includes metal oxide.   
     
     
       9. The semiconductor memory device of  claim 8 , wherein at least one of the plurality of layers includes aluminum oxide, hafnium oxide or lanthanum oxide. 
     
     
       10. The semiconductor memory device of  claim 8 , wherein the plurality of layers includes a first layer having aluminum oxide and a second layer having oxide. 
     
     
       11. The semiconductor memory device of  claim 8 , wherein the blocking insulation layer includes an insulation material having a higher dielectric constant than the tunnel insulation layer. 
     
     
       12. The semiconductor memory device of  claim 8 , further comprising:
 a first selection gate pattern disposed between the substrate and a lowermost one of the insulation patterns; and   a second selection gate pattern disposed on an uppermost one of the insulation patterns.   
     
     
       13. A semiconductor memory device comprising:
 a substrate;   a first insulation pattern disposed on the substrate;   a first selection gate pattern disposed on the first insulation pattern;   a plurality of second insulation patterns and a plurality of cell gate patterns that are alternately stacked on the first selection gate pattern;   an active pattern disposed on the substrate and extending upward along sidewalls of the plurality of second insulation patterns and sidewalls of the plurality of cell gate patterns;   a blocking insulation layer disposed on the sidewalls of the plurality of second insulation patterns and the sidewalls of the plurality of cell gate patterns;   a charge storage layer disposed on a sidewall of the blocking insulation layer;   a tunnel insulation layer disposed on a sidewall of the charge storage layer and disposed between the charge storage layer and the active pattern;   a conductive barrier disposed between the blocking insulation layer and the sidewall of one of the plurality of cell gate patterns, and including nitrogen; and   a second selection gate pattern disposed on an uppermost one of the plurality of second insulation patterns,   wherein the charge storage layer is disposed between the blocking insulation layer and the tunnel insulation layer,   wherein the blocking insulation layer is disposed between the charge storage layer and the sidewalls of the plurality of second insulation patterns and between the charge storage layer and the sidewalls of the plurality of cell gate patterns, and   wherein the blocking insulation layer includes aluminum oxide, hafnium oxide or lanthanum oxide.   
     
     
       14. The semiconductor memory device of  claim 13 , wherein the blocking insulation layer includes a plurality of layers. 
     
     
       15. The semiconductor memory device of  claim 13 , wherein the blocking insulation layer includes a first layer having aluminum oxide and a second layer having oxide. 
     
     
       16. The semiconductor memory device of  claim 13 , wherein the blocking insulation layer includes an insulation material having a higher dielectric constant than the tunnel insulation layer. 
     
     
       17. A semiconductor memory device comprising:
 a substrate;   a plurality of insulation patterns and a plurality of cell gate patterns that are alternately stacked on the substrate;   an active pattern disposed on the substrate and extending upward along sidewalls of the plurality of insulation patterns and sidewalls of the plurality of cell gate patterns;   a blocking insulation layer disposed on the sidewalls of the plurality of insulation patterns and the sidewalls of the plurality of cell gate patterns;   a charge storage layer disposed on a sidewall of the blocking insulation layer;   a tunnel insulation layer disposed on a sidewall of the charge storage layer and disposed between the charge storage layer and the active pattern; and   a conductive barrier disposed between the blocking insulation layer and the sidewall of one of the plurality of cell gate patterns, and including nitrogen,   wherein the charge storage layer is disposed between the blocking insulation layer and the tunnel insulation layer,   wherein the blocking insulation layer is disposed between the charge storage layer and the sidewalls of the plurality of insulation patterns and between the charge storage layer and the sidewalls of the plurality of cell gate patterns,   wherein each of the plurality of cell gate patterns has a planar surface,   wherein the active pattern is enclosed by the plurality of insulation patterns and the plurality of cell gate patterns, and   wherein the blocking insulation layer includes an insulation material having a higher dielectric constant than the tunnel insulation layer.   
     
     
       18. The semiconductor memory device of  claim 17 , wherein the blocking insulation layer includes a plurality of layers, and includes metal oxide. 
     
     
       19. The semiconductor memory device of  claim 17 , wherein a cross section of the active pattern is square-shaped, circle-shaped, oval-shaped, or polygon-shaped.