Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

Abstract

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

What is claimed is: 
     
         1 . A memory controller comprising:
 a controller input/output circuit configured to output a first command to read first data from a memory device, and output a second command to read an error corrected data of the first data from the memory device; and   a correction status information receiver configured to receive correction status information from the memory device while reading the first data from the memory device,   wherein the controller input/output circuit outputs the second command in response to the received correction status information, the correction status information indicating whether a number of error bits in the first data is greater than or equal to a threshold value, and the controller input/output circuit further outputs at least one additional command between the first command and the second command.   
     
     
         2 . The memory controller of  claim 1 , wherein the controller input/output circuit is further configured to output a first address information associated with the first data and to output a second address information associated with the error corrected data of the first data. 
     
     
         3 . The memory controller of  claim 2 , the second address information is same with the first address information. 
     
     
         4 . The memory controller of  claim 2 , wherein the second command is a buffer read command to read the error corrected data of the first data stored in a buffer, and the second address information which indicates a location of the error corrected data of the first data in the buffer is different from the first address information. 
     
     
         5 . The memory controller of  claim 1 , wherein the at least one additional command initiates a memory operation of the memory device while the memory device is correcting errors of the first data, and completes the memory operation before outputting the second command. 
     
     
         6 . The memory controller of  claim 5 , wherein the at least one additional command is one of row activation command, row pre-charge command, data read command and data write command. 
     
     
         7 . The memory controller of  claim 1 , wherein a time delay between the first command and the second command is longer than an error correction time required to correct error detected in the first data. 
     
     
         8 . The memory controller of  claim 1 , wherein the controller input/output circuit does not output the second command if the correction status information indicates that the number of error bits in the first data is smaller than the threshold value. 
     
     
       9. A memory device configured to communicate with a memory controller, the memory device comprising:
 a first storage region;   a second storage region;   an error correction circuit configured to correct errors with respect to first data using an error correction operation;   an error detector configured to detect a number of error bits in the first data and output a detection signal based on a detection result; and   a data output circuit configured to output corrected data that is corrected by the error correction circuit,   wherein the error correction operation includes a first error correction operation and a second error correction operation that employs a different error correction capability from the first error correction operation,   in response to detecting that the number of error bits in the first data stored in the first storage region does not exceed a threshold value, i) the error correction circuit is configured to read the first data from the first storage region according to the first error correction operation, and ii) the data output circuit is configured to output the first data without storing the first data in the second storage region, and   in response to detecting that the number of error bits in the first data stored in the first storage region exceeds the threshold value, i) second data is stored in the second storage region based on the first data, ii) the error correction circuit is configured to read the second data from the second storage region according to the second error correction operation, and iii) the data output circuit is configured to output the second data.    
     
     
       10. The memory device of  claim 9 , wherein the errors with respect to the first data is corrected using the error correction operation capable of correcting the number of error bits up to the threshold value.  
     
     
       11. The memory device of  claim 9 , wherein
 the first error correction operation is configured to correct the number of error bits in the first data up to a first error correction capability, and   the second error correction operation is configured to correct the number of error bits in the first data up to a second error correction capability.    
     
     
       12. The memory device of  claim 9 , wherein
 the first error correction operation is configured to produce first corrected data and present the first corrected data as output data, when the number of error bits in the first data does not exceed the threshold value.    
     
     
       13. A memory device configured to communicate with a memory controller, the memory device comprising:
 a first storage region;   a second storage region;   an error correction circuit configured to correct errors with respect to first data using an error correction operation;   an error detector configured to detect a number of error bits in the first data and output a detection signal based on a detection result; and   a data output circuit configured to output corrected data that is corrected by the error correction circuit,   wherein the error correction operation includes a first error correction operation and a second error correction operation that employs a greater error correction capability from the first error correction operation,   in response to detecting that the number of error bits in the first data stored in the first storage region does not exceed a threshold value, i) the error correction circuit is configured to read the first data from the first storage region according to the first error correction operation, and ii) the data output circuit is configured to output the first data without storing the first data in the second storage region,   in response to detecting that the number of error bits in the first data stored in the first storage region exceeds the threshold value, i) second data is stored in the second storage region based on the first data, ii) the error correction circuit is configured to read the second data from the second storage region according to the second error correction operation, and iii) the data output circuit is configured to output the second data and   the threshold value includes the number of error bits that is at least one error bit less than an error correction limit of the first error correction operation.    
     
     
       14. The memory device of  claim 13 , wherein among the first data corresponding to a first address and the second data corresponding to a second address, the second data is read and output when the number of error bits in the first data exceeds the threshold value.  
     
     
       15. The memory device of  claim 13 , wherein
 the first error correction operation is configured to correct the number of error bits in the first data up to a first error correction capability, and   the second error correction operation is configured to correct the number of error bits in the first data up to a second error correction capability.    
     
     
       16. A memory device configured to communicate with a memory controller, the memory device comprising:
 a first storage region;   a second storage region;   an error correction circuit configured to correct errors with respect to first data using an error correction operation;   an error detector configured to detect a number of error bits in the first data and output a detection signal based on a detection result; and   a data output circuit configured to output corrected data that is corrected by the error correction circuit,   wherein the error correction operation includes a first error correction operation having a first error correction capability and a second error correction operation having a second error correction capability that is different from the first error correction capability,   in response to detecting that the number of error bits falls below a threshold value, i) the error correction circuit is configured to read the first data from the first storage region according to the first error correction operation, and ii) the data output circuit is configured to output the first data without storing the first data in the second storage region, and   in response to detecting that the number of error bits exceeds the threshold value, the error correction circuit is configured to correct the errors on the first data, i) the error correction circuit is configured to read, according to the second error correction operation, second data that is stored in the second storage region based on the first data, and ii) the data output circuit is configured to output the second data.    
     
     
       17. The memory device of  claim 16 , wherein
 the first error correction operation is configured to correct the number of error bits in the first data up to the first error correction capability, and   the second error correction operation is configured to correct the number of error bits in the first data up to the second error correction capability.    
     
     
       18. The memory device of  claim 16 , further comprising:
 a correction status information generator configured to output correction status information associated with the first data, the correction status information indicating whether the number of error bits is greater than or equal to the threshold value.    
     
     
       19. The memory device of  claim 16 , wherein the memory device is configured to receive a command from an external device and perform a memory operation, in response to the command before output data is sent to the external device.