Inventor · disambiguated record
Gayle W. Miller
Also filed as: MILLER GAYLE · MILLER GAYLE W · MILLER GAYLE W JR · MILLER JR GAYLE W
63 granted patents·11 pending applications·1,350 citations·filing 1985–2011
99Inventor score
Files withLSI LOGIC CORP26ATMEL CORP16HYUNDAI ELECTRONICS AMERICA8NCR CO8AT & T GLOBAL INF SOLUTION7
Top patents by PatentIndex Score
74 records- 0195US7435661B2Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolationATMEL CORP·Filed 2006·Granted Oct 14, 2008·56 cites·25 claims
- 0294US5459501ASolid-state ink-jet print headAT & T GLOBAL INF SOLUTION·Filed 1993·Granted Oct 17, 1995·84 cites·15 claims
- 0393US7348256B2Methods of forming reduced electric field DMOS using self-aligned trench isolationATMEL CORP·Filed 2005·Granted Mar 25, 2008·20 cites·21 claims
- 0493US6441419B1Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing sameLSI LOGIC CORP·Filed 2000·Granted Aug 27, 2002·91 cites·20 claims
- 0590US4703551AProcess for forming LDD MOS/CMOS structuresNCR CO·Filed 1986·Granted Nov 3, 1987·71 cites·7 claims
- 0688US7402846B2Electrostatic discharge (ESD) protection structure and a circuit using the sameATMEL CORP·Filed 2005·Granted Jul 22, 2008·17 cites·9 claims
- 0786US5821572ASimple BICMOS process for creation of low trigger voltage SCR and zener diode pad protectionSYMBIOS INC·Filed 1996·Granted Oct 13, 1998·60 cites·17 claims
- 0886US5581861AMethod for making a solid-state ink jet print headAT & T GLOBAL INF SOLUTION·Filed 1995·Granted Dec 10, 1996·49 cites·3 claims
- 0984US6130117ASimple bicmos process for creation of low trigger voltage SCR and zener diode pad protectionLSI LOGIC CORP·Filed 1998·Granted Oct 10, 2000·53 cites·6 claims
- 1082US6277707B1Method of manufacturing semiconductor device having a recessed gate structureLSI LOGIC CORP·Filed 1998·Granted Aug 21, 2001·58 cites·28 claims
- 1182US4654121AFabrication process for aligned and stacked CMOS devicesNCR CO·Filed 1986·Granted Mar 31, 1987·45 cites·10 claims
- 1282US4647340AProgrammable read only memory using a tungsten fuseNCR CO·Filed 1986·Granted Mar 3, 1987·63 cites·7 claims
- 1381US8378414B2Low leakage FINFETsATMEL CORP·Filed 2011·Granted Feb 19, 2013·5 cites·13 claims
- 1479US6383332B1Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpointLSI LOGIC CORP·Filed 2000·Granted May 7, 2002·20 cites·7 claims
- 1579US6057571AHigh aspect ratio, metal-to-metal, linear capacitor for an integrated circuitLSI LOGIC CORP·Filed 1998·Granted May 2, 2000·58 cites·18 claims
- 1678US6794310B1Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereofLSI LOGIC CORP·Filed 2001·Granted Sep 21, 2004·17 cites·14 claims
- 1776US6358819B1Dual gate oxide process for deep submicron ICSLSI LOGIC CORP·Filed 1998·Granted Mar 19, 2002·32 cites·33 claims
- 1875US6885078B2Circuit isolation utilizing MeV implantationLSI LOGIC CORP·Filed 2001·Granted Apr 26, 2005·19 cites·11 claims
- 1975US6258205B1Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst materialLSI LOGIC CORP·Filed 2000·Granted Jul 10, 2001·17 cites·8 claims
- 2073US4648175AUse of selectively deposited tungsten for contact formation and shunting metallizationNCR CO·Filed 1985·Granted Mar 10, 1987·44 cites·10 claims
- 2172US6063672ANMOS electrostatic discharge protection device and method for CMOS integrated circuitLSI LOGIC CORP·Filed 1999·Granted May 16, 2000·31 cites·11 claims
- 2271US5821013AVariable step height control of lithographic patterning through transmitted light intensity variationSYMBIOS INC·Filed 1996·Granted Oct 13, 1998·30 cites·29 claims
- 2369US7407851B2DMOS device with sealed channel processingMILLER GAYLE W·Filed 2006·Granted Aug 5, 2008·4 cites·30 claims
- 2468US4679299AFormation of self-aligned stacked CMOS structures by lift-offNCR CO·Filed 1986·Granted Jul 14, 1987·25 cites·18 claims
- 2565US6080670AMethod of detecting a polishing endpoint layer of a semiconductor wafer which includes a non-reactive reporting specieLSI LOGIC CORP·Filed 1998·Granted Jun 27, 2000·31 cites·20 claims
- 2665US5438022AMethod for using low dielectric constant material in integrated circuit fabricationAT & T GLOBAL INF SOLUTION·Filed 1993·Granted Aug 1, 1995·20 cites·4 claims
- 2764US7521312B2Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor deviceATMEL CORP·Filed 2007·Granted Apr 21, 2009·2 cites·19 claims
- 2863US4682404AMOSFET process using implantation through siliconNCR CO·Filed 1986·Granted Jul 28, 1987·30 cites·6 claims
- 2962US6090724AMethod for composing a thermally conductive thin film having a low dielectric propertyLSI LOGIC CORP·Filed 1998·Granted Jul 18, 2000·25 cites·7 claims
- 3061US6319793B1Circuit isolation utilizing MeV implantationLSI LOGIC CORP·Filed 1999·Granted Nov 20, 2001·18 cites·21 claims
- 3160US6522005B1Integrated circuit device comprising low dielectric constant material for reduced cross talkHYUNDAI ELECTRONICS AMERICA·Filed 2000·Granted Feb 18, 2003·5 cites·7 claims
- 3259US6071818AEndpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst materialLSI LOGIC CORP·Filed 1998·Granted Jun 6, 2000·22 cites·9 claims
- 3357US6117779AEndpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpointLSI LOGIC CORP·Filed 1998·Granted Sep 12, 2000·17 cites·13 claims
- 3456US7629649B2Method and materials to control doping profile in integrated circuit substrate materialATMEL CORP·Filed 2006·Granted Dec 8, 2009·1 cites·13 claims
- 3556US6328802B1Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereofLSI LOGIC CORP·Filed 1999·Granted Dec 11, 2001·17 cites·7 claims
- 3656US5672905ASemiconductor fuse and methodAT & T GLOBAL INF SOLUTION·Filed 1992·Granted Sep 30, 1997·23 cites·8 claims
- 3754US6448653B1Method for using low dielectric constant material in integrated circuit fabricationHYUNDAI ELECTRONICS AMERICA·Filed 2000·Granted Sep 10, 2002·3 cites·7 claims
- 3854US6136719AMethod and arrangement for fabricating a semiconductor deviceLSI LOGIC CORP·Filed 1999·Granted Oct 24, 2000·18 cites·20 claims
- 3953US6011283APillar emitter for BiCMOS devicesHYUNDAI ELECTRONICS AMERICA·Filed 1992·Granted Jan 4, 2000·15 cites·6 claims
- 4052US5447880AMethod for forming an amorphous silicon programmable elementAT & T GLOBAL INF SOLUTION·Filed 1994·Granted Sep 5, 1995·20 cites·14 claims
- 4152US2006124747A1Protective envelope for a chip cardRATHBUN IRWIN D·Filed 2004·Application pending·0 cites
- 4252US2007207589A1Registration mark within an overlap of dopant regionsATMEL CORP·Filed 2007·Application pending·0 cites
- 4352US2008290426A1Dmos device with sealed channel processingATMEL CORP·Filed 2008·Application pending·0 cites
- 4451US7230342B2Registration mark within an overlap of dopant regionsATMEL CORP·Filed 2005·Granted Jun 12, 2007·0 cites·5 claims
- 4551US6806162B1Method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor deviceLSI LOGIC CORP·Filed 2003·Granted Oct 19, 2004·3 cites·5 claims
- 4650US7848070B2Electrostatic discharge (ESD) protection structure and a circuit using the sameATMEL CORP·Filed 2008·Granted Dec 7, 2010·0 cites·20 claims
- 4750US6504250B1Integrated circuit device with reduced cross talkHYUNDAI ELECTRONICS AMERICA·Filed 2000·Granted Jan 7, 2003·2 cites·7 claims
- 4850US6358837B1Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuitLSI LOGIC CORP·Filed 1998·Granted Mar 19, 2002·16 cites·19 claims
- 4950US2008135933A1Reduced electric field dmos using self-aligned trench isolationATMEL CORP·Filed 2008·Application pending·0 cites
- 5050US2008173940A1Reduced electric field dmos using self-aligned trench isolationATMEL CORP·Filed 2008·Application pending·0 cites
Showing the top 50 of 74 patent records by PatentIndex Score.
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