Inventor

LANGENDORF BRIAN K

US39 patents

⚠️ This page may combine multiple inventors who share the name “LANGENDORF BRIAN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LANGENDORF BRIAN K

INTEL CORP

Method and apparatus for arbitrating between command streams

Virtual PCI device apparatus and method

System for delaying dequeue of commands received prior to fence command until commands received before fence command are ordered for execution in a fixed sequence

High-throughput interconnect allowing bus transactions based on partial access requests

Upgrading an integrated graphics subsystem

Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel

Method and apparatus for improving system performance when reordering commands

Programmable secondary clock generator

System and method for placement of operands in system memory

Method and apparatus for blending bus writes and cache write-backs to memory

Method and apparatus for initializing data structures to accelerate variable length decode

Symmetrical accelerated graphics port (AGP)

Method and apparatus to control device temperature

Method and apparatus for accelerating software decode of variable length encoded information

Method and apparatus for implementing a flush command for an accelerated graphics port device

Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory

Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics

Method and apparatus for avoiding deadlock in the issuance of commands that are reordered and require data movement according to an original command order

Low load host/PCI bus bridge

Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme

Performing speculative system memory reads prior to decoding device code

Computer system including an apparatus for reducing power consumption in an on-chip tag static RAM

Method and apparatus for reducing power in on-chip tag SRAM

Memory controller hub

Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock

Method and apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock

Method and apparatus for streamlined handshaking between state machines

Method and apparatus for automatically detecting whether a board level cache is implemented with Mcache

Method and apparatus for automatically detecting a selected cache type

PRIME COMPUTER INC

Method and apparatus for indexing, accessing and updating a memory

Method and apparatus for qualifying branch cache entries

System bus for multiprocessor computer system

Branch cache system with instruction boundary determination independent of parcel boundary

Hashing indexer for branch cache

NVIDIA CORP

Apparatus, system, and method for Z-culling

Apparatus, system, and method for avoiding data writes that stall transactions in a bus interface

Apparatus, system, and method for Z-culling

Method and system for maintaining shadow copies of data using a shadow mask bit

INTEL CORPORAITON

Method and apparatus for combining multiple writes to a memory resource utilizing a write buffer