Inventor · disambiguated record
Venkat R. Kolagunta
Also filed as: KOLAGUNTA VENKAT · KOLAGUNTA VENKAT R
25 granted patents·5 pending applications·463 citations·filing 1999–2011
96Inventor score
Top patents by PatentIndex Score
30 records- 0195US7410876B1Methodology to reduce SOI floating-body effectFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 12, 2008·31 cites·19 claims
- 0295US7018901B1Method for forming a semiconductor device having a strained channel and a heterojunction source/drainFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Mar 28, 2006·105 cites·24 claims
- 0392US6444569B2Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 2001·Granted Sep 3, 2002·60 cites·29 claims
- 0491US7799650B2Method for making a transistor with a stressorFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 21, 2010·27 cites·16 claims
- 0590US7323373B2Method of forming a semiconductor device with decreased undercutting of semiconductor materialFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 29, 2008·22 cites·3 claims
- 0687US7420202B2Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic deviceFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Sep 2, 2008·13 cites·12 claims
- 0787US7067868B2Double gate device having a heterojunction source/drain and strained channelFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 27, 2006·39 cites·17 claims
- 0885US6274478B1Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 1999·Granted Aug 14, 2001·70 cites·9 claims
- 0983US7727870B2Method of making a semiconductor device using a stressorFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 1, 2010·13 cites·16 claims
- 1080US7514313B2Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layerFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 7, 2009·9 cites·20 claims
- 1179US6573173B2Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) processMOTOROLA INC·Filed 2002·Granted Jun 3, 2003·23 cites·3 claims
- 1277US7282426B2Method of forming a semiconductor device having asymmetric dielectric regions and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 16, 2007·5 cites·18 claims
- 1376US7504289B2Process for forming an electronic device including transistor structures with sidewall spacersFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Mar 17, 2009·7 cites·7 claims
- 1475US7714318B2Electronic device including a transistor structure having an active region adjacent to a stressor layerFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted May 11, 2010·5 cites·20 claims
- 1574US7470624B2Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Dec 30, 2008·4 cites·20 claims
- 1669US7678698B2Method of forming a semiconductor device with multiple tensile stressor layersFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 16, 2010·3 cites·18 claims
- 1769US7479465B2Transfer of stress to a layerFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jan 20, 2009·3 cites·12 claims
- 1868US7843011B2Electronic device including insulating layers having different strainsFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Nov 30, 2010·2 cites·20 claims
- 1965US7161199B2Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 9, 2007·12 cites·26 claims
- 2062US7534674B2Method of making a semiconductor device with a stressorFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 19, 2009·1 cites·19 claims
- 2161US7144784B2Method of forming a semiconductor device and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Dec 5, 2006·9 cites·21 claims
- 2251US2008173957A1Method of forming a semiconductor device having a symmetric dielectric regions and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2348US8021957B2Process of forming an electronic device including insulating layers having different strainsFREESCALE SEMICONDUCTOR INC·Filed 2010·Granted Sep 20, 2011·0 cites·20 claims
- 2447US7565639B2Integrated assist features for epitaxial growth bulk tiles with compensationFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jul 21, 2009·0 cites·20 claims
- 2542US7560318B2Process for forming an electronic device including semiconductor layers having different stressesFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 14, 2009·0 cites·20 claims
- 2641US8741743B2Integrated assist features for epitaxial growthZIA OMAR·Filed 2007·Granted Jun 3, 2014·0 cites·19 claims
- 2739US2007249127A1Electronic device including a semiconductor layer and a sidewall spacer and a process of forming the sameFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 2839US2008026517A1Method for forming a stressor layerGRUDOWSKI PAUL A·Filed 2006·Application pending·0 cites
- 2937US2012302022A1Method for forming an asymmetric semiconductor deviceKOLAGUNTA VENKAT R·Filed 2011·Application pending·0 cites
- 3036US2006043500A1Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereofCHEN JIAN·Filed 2004·Application pending·0 cites
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