Inventor · disambiguated record
Kamalesh K. Srivastava
Also filed as: SRIVASTAVA KAMALESH · SRIVASTAVA KAMALESH K
38 granted patents·8 pending applications·1,014 citations·filing 1990–2019
98Inventor score
Top patents by PatentIndex Score
46 records- 0197US6531069B1Reactive Ion Etching chamber design for flip chip interconnectionsIBM·Filed 2000·Granted Mar 11, 2003·144 cites·16 claims
- 0294US9472520B2Multilayer pillar for reduced stress interconnect and method of making sameJADHAV VIRENDRA R·Filed 2012·Granted Oct 18, 2016·14 cites·19 claims
- 0394US5130779ASolder mass having conductive encapsulating arrangementIBM·Filed 1990·Granted Jul 14, 1992·185 cites·47 claims
- 0493US11244917B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2019·Granted Feb 8, 2022·4 cites·11 claims
- 0592US5251806AMethod of forming dual height solder interconnectionsIBM·Filed 1992·Granted Oct 12, 1993·144 cites·48 claims
- 0691US10403590B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2017·Granted Sep 3, 2019·4 cites·9 claims
- 0790US6622907B2Sacrificial seed layer process for forming C4 solder bumpsIBM·Filed 2002·Granted Sep 23, 2003·78 cites·20 claims
- 0890US6293457B1Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallizationIBM·Filed 2000·Granted Sep 25, 2001·86 cites·23 claims
- 0990US5800626AControl of gas content in process liquids for improved megasonic cleaning of semiconductor wafers and microelectronics substratesIBM·Filed 1997·Granted Sep 1, 1998·142 cites·14 claims
- 1088US10396051B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2017·Granted Aug 27, 2019·3 cites·13 claims
- 1187US8293587B2Multilayer pillar for reduced stress interconnect and method of making sameJADHAV VIRENDRA R·Filed 2007·Granted Oct 23, 2012·9 cites·19 claims
- 1282US7144490B2Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layerIBM·Filed 2003·Granted Dec 5, 2006·14 cites·7 claims
- 1382US6661100B1Low impedance power distribution structure for a semiconductor chip packageIBM·Filed 2002·Granted Dec 9, 2003·32 cites·20 claims
- 1472US7473997B2Method for forming robust solder interconnect structures by reducing effects of seed layer underetchingIBM·Filed 2005·Granted Jan 6, 2009·4 cites·10 claims
- 1571US5048744APalladium enhanced fluxless soldering and bonding of semiconductor device contactsIBM·Filed 1990·Granted Sep 17, 1991·47 cites·19 claims
- 1669US8493746B2Additives for grain fragmentation in Pb-free Sn-based solderARVIN CHARLES L·Filed 2010·Granted Jul 23, 2013·2 cites·14 claims
- 1768US11094657B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2019·Granted Aug 17, 2021·0 cites·14 claims
- 1866US11171102B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2019·Granted Nov 9, 2021·0 cites·13 claims
- 1966US7425278B2Process of etching a titanium/tungsten surface and etchant used thereinIBM·Filed 2006·Granted Sep 16, 2008·2 cites·6 claims
- 2066US6221780B1Dual damascene flowable oxide insulation structure and metallic barrierIBM·Filed 1999·Granted Apr 24, 2001·27 cites·26 claims
- 2165US8314500B2Interconnections for flip-chip using lead-free solders and having improved reaction barrier layersBELANGER LUC·Filed 2006·Granted Nov 20, 2012·4 cites·1 claims
- 2264US8197612B2Optimization of metallurgical properties of a solder jointBUSBY JAMES A·Filed 2008·Granted Jun 12, 2012·2 cites·15 claims
- 2362US9640501B2Multilayer pillar for reduced stress interconnect and method of making sameIBM·Filed 2014·Granted May 2, 2017·0 cites·19 claims
- 2462US6995475B2I/C chip suitable for wire bondingIBM·Filed 2003·Granted Feb 7, 2006·9 cites·3 claims
- 2561US6995084B2Method for forming robust solder interconnect structures by reducing effects of seed layer underetchingIBM·Filed 2004·Granted Feb 7, 2006·7 cites·12 claims
- 2660US7952207B2Flip-chip assembly with organic chip carrier having mushroom-plated solder resist openingIBM·Filed 2007·Granted May 31, 2011·2 cites·15 claims
- 2760US7784669B2Method and process for reducing undercooling in a lead-free tin-rich solder alloyIBM·Filed 2009·Granted Aug 31, 2010·1 cites·11 claims
- 2860US6727589B2Dual damascene flowable oxide insulation structure and metallic barrierIBM·Filed 2000·Granted Apr 27, 2004·6 cites·24 claims
- 2959US7932169B2Interconnection for flip-chip using lead-free solders and having improved reaction barrier layersIBM·Filed 2009·Granted Apr 26, 2011·1 cites·3 claims
- 3059US7703661B2Method and process for reducing undercooling in a lead-free tin-rich solder alloyIBM·Filed 2007·Granted Apr 27, 2010·1 cites·22 claims
- 3156US9111816B2Multilayer pillar for reduced stress interconnect and method of making sameJADHAV VIRENDRA R·Filed 2012·Granted Aug 18, 2015·0 cites·18 claims
- 3253US8910853B2Additives for grain fragmentation in Pb-free Sn-based solderIBM·Filed 2013·Granted Dec 16, 2014·0 cites·17 claims
- 3352US6479884B2Interim oxidation of silsesquioxane dielectric for dual damascene processIBM·Filed 2001·Granted Nov 12, 2002·4 cites·4 claims
- 3448US6348736B1In situ formation of protective layer on silsesquioxane dielectric for dual damascene processIBM·Filed 1999·Granted Feb 19, 2002·13 cites·14 claims
- 3547US2009197114A1Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder jointsSHIH DA-YUAN·Filed 2008·Application pending·0 cites
- 3647US2009197103A1Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder jointsSHIH DA-YUAN·Filed 2008·Application pending·0 cites
- 3747US2011195543A1Flip-chip assembly with organic chip carrier having mushroom-plated solder resist openingIBM·Filed 2011·Application pending·0 cites
- 3846US7572726B2Method of forming a bond pad on an I/C chip and resulting structureIBM·Filed 2005·Granted Aug 11, 2009·0 cites·15 claims
- 3946US2006249854A1Device with area array pads for test probingCHENG TIEN-JEN·Filed 2006·Application pending·0 cites
- 4045US7767575B2Forming robust solder interconnect structures by reducing effects of seed layer underetchingTESSERA INTELLECTUAL PROPERTIE·Filed 2009·Granted Aug 3, 2010·0 cites·5 claims
- 4145US6329280B1Interim oxidation of silsesquioxane dielectric for dual damascene processIBM·Filed 1999·Granted Dec 11, 2001·10 cites·18 claims
- 4245US2008119056A1Method for improved copper layer etching of wafers with c4 connection structuresIBM·Filed 2006·Application pending·0 cites
- 4343US5225711APalladium enhanced soldering and bonding of semiconductor device contactsIBM·Filed 1991·Granted Jul 6, 1993·13 cites·9 claims
- 4440US2007080455A1Semiconductors and methods of makingIBM·Filed 2005·Application pending·0 cites
- 4540US2005167837A1Device with area array pads for test probingIBM·Filed 2004·Application pending·0 cites
- 4634US2002190028A1Method of improving uniformity of etching of a film on an articleIBM·Filed 2001·Application pending·0 cites
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