Inventor

MACWILLIAMS PETER D

US51 patents

⚠️ This page may combine multiple inventors who share the name “MACWILLIAMS PETER D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MACWILLIAMS PETER D

INTEL CORP

Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system

Method and apparatus for implementing multiple memory buses on a memory module

Method for implementing multiple memory buses on a memory module

Method and apparartus for sharing a signal line between agents

Method and apparatus for performing deferred transactions

Memory expansion channel for propagation of control and request packets

Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines

Highly pipelined bus architecture

Method and apparatus for performing deferred transactions

Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus

Method and apparatus for sharing a signal line between agents

Scalable cache attributes for an input/output bus

Second level cache controller unit and system

Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path

Scalable, high bandwidth multicard memory system utilizing a single memory controller

Method and apparatus for performing deferred transactions

Method and apparatus for ordering writeback data transfers on a bus

Method and apparatus for changing data transfer widths in a computer system

Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation

Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit

Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment

System resource arbitration mechanism for a host bridge

Independent timing compensation of write data path and read data path on a common data bus

Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

Method and apparatus for executing multiple transactions within a single arbitration cycle

Low load host/PCI bus bridge

Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge

Asynchronous modular bus architecture with cache consistency

Method and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system reset

Optimized write protocol for memory accesses utilizing row and column strobes

Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system

Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus

Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system

Method and apparatus for detecting errors in data output from memory and a device failure in the memory

Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth

System resource arbitration mechanism for a host bridge

Data flow control mechanism for a bus supporting two-and three-agent transactions

Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer

Method and apparatus for retrieving data from a data storage device

Multi-mode microprocessor having a pin for resetting its register without purging its cache

Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol

Two strobed memory access

Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing system

Parallel multistage synchronization method and apparatus

Method and apparatus for supporting multiple overlapping address spaces on a shared bus

Method and apparatus for supporting multiple overlapping address spaces on a shared bus

Internally controlled signal system for controlling the operation of a device

Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

RAMBUS INC

High performance cost optimized memory with delayed memory writes

Apparatus and method for bus timing compensation