Inventor · disambiguated record
Gary N. Hammond
Also filed as: HAMMOND GARY · HAMMOND GARY N · HAMMOND GARY NEIL
54 granted patents·3 pending applications·3,244 citations·filing 1988–2012
99Inventor score
Technology areasG06F
Top patents by PatentIndex Score
57 records- 0195US5638525AProcessor capable of executing programs that contain RISC and CISC instructionsINTEL CORP·Filed 1995·Granted Jun 10, 1997·266 cites·19 claims
- 0294US6430670B1Apparatus and method for a virtual hashed page tableHEWLETT PACKARD CO·Filed 2000·Granted Aug 6, 2002·86 cites·26 claims
- 0394US6408386B1Method and apparatus for providing event handling functionality in a computer systemINTEL CORP·Filed 2001·Granted Jun 18, 2002·90 cites·15 claims
- 0493US5860017AProcessor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instructionINTEL CORP·Filed 1996·Granted Jan 12, 1999·182 cites·29 claims
- 0589US6065105ADependency matrixINTEL CORP·Filed 1997·Granted May 16, 2000·169 cites·16 claims
- 0689US5918251AMethod and apparatus for preloading different default address translation attributesINTEL CORP·Filed 1996·Granted Jun 29, 1999·151 cites·18 claims
- 0787US6088780APage table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jul 11, 2000·141 cites·35 claims
- 0887US6016540AMethod and apparatus for scheduling instructions in wavesINTEL CORP·Filed 1997·Granted Jan 18, 2000·136 cites·18 claims
- 0985US7392369B2Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation checkINTEL CORP·Filed 2006·Granted Jun 24, 2008·14 cites·24 claims
- 1085US6711653B1Flexible mechanism for enforcing coherency among caching structuresINTEL CORP·Filed 2000·Granted Mar 23, 2004·39 cites·20 claims
- 1185US5740413AMethod and apparatus for providing address breakpoints, branch breakpoints, and single steppingINTEL CORP·Filed 1997·Granted Apr 14, 1998·120 cites·17 claims
- 1284US7383374B2Method and apparatus for managing virtual addressesINTEL CORP·Filed 2005·Granted Jun 3, 2008·14 cites·28 claims
- 1384US5774686AMethod and apparatus for providing two system architectures in a processorINTEL CORP·Filed 1995·Granted Jun 30, 1998·104 cites·66 claims
- 1484US5659679AMethod and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer systemINTEL CORP·Filed 1995·Granted Aug 19, 1997·118 cites·15 claims
- 1584US5621886AMethod and apparatus for providing efficient software debuggingINTEL CORP·Filed 1995·Granted Apr 15, 1997·116 cites·34 claims
- 1683US6393544B1Method and apparatus for calculating a page table index from a virtual addressINST THE DEV OF EMERGING ARCHI·Filed 1999·Granted May 21, 2002·113 cites·20 claims
- 1782US5752275ATranslation look-aside buffer including a single page size translation unitINTEL CORP·Filed 1997·Granted May 12, 1998·96 cites·20 claims
- 1880US6065115AProcessor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instructionINTEL CORP·Filed 1998·Granted May 16, 2000·78 cites·31 claims
- 1979US7263567B1Method and apparatus for lowering the die temperature of a microprocessor and maintaining the temperature below the die burn outINTEL CORP·Filed 2000·Granted Aug 28, 2007·43 cites·15 claims
- 2079US5940872ASoftware and hardware-managed translation lookaside bufferINTEL CORP·Filed 1996·Granted Aug 17, 1999·89 cites·20 claims
- 2177US6199144B1Method and apparatus for transferring data in a computer systemINTEL CORP·Filed 1997·Granted Mar 6, 2001·77 cites·20 claims
- 2276US6430657B1Computer system that provides atomicity by using a tlb to indicate whether an exportable instruction should be executed using cache coherency or by exporting the exportable instruction, and emulates instructions specifying a bus lockINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Aug 6, 2002·80 cites·6 claims
- 2374US6397301B1Preventing access to secure area of a cacheINTEL CORP·Filed 1999·Granted May 28, 2002·68 cites·27 claims
- 2474US6128706AApparatus and method for a load bias--load with intent to semaphoreINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 3, 2000·68 cites·15 claims
- 2573US6560689B1TLB using region ID prevalidationINTEL CORP·Filed 2000·Granted May 6, 2003·19 cites·24 claims
- 2673US6209085B1Method and apparatus for performing process switching in multiprocessor computer systemsINTEL CORP·Filed 1997·Granted Mar 27, 2001·64 cites·21 claims
- 2773US5918250AMethod and apparatus for preloading default address translation attributesINTEL CORP·Filed 1995·Granted Jun 29, 1999·65 cites·20 claims
- 2871US6542981B1Microcode upgrade and special function support by executing RISC instruction to invoke resident microcodeINTEL CORP·Filed 1999·Granted Apr 1, 2003·57 cites·24 claims
- 2970US7330963B2Resolving all previous potentially excepting architectural operations before issuing store architectural operationINTEL CORP·Filed 2006·Granted Feb 12, 2008·4 cites·11 claims
- 3070US6219774B1Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architectureINTEL CORP·Filed 1998·Granted Apr 17, 2001·48 cites·14 claims
- 3170US5809563AMethod and apparatus utilizing a region based page table walk bitINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Sep 15, 1998·43 cites·13 claims
- 3269US6408373B2Method and apparatus for pre-validating regions in a virtual addressing schemeINST THE DEV OF EMERGING ARCHI·Filed 2001·Granted Jun 18, 2002·12 cites·7 claims
- 3369US6012132AMethod and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page tableINTEL CORP·Filed 1997·Granted Jan 4, 2000·53 cites·28 claims
- 3466US6584558B2Article for providing event handling functionality in a processor supporting different instruction setsINTEL CORP·Filed 2002·Granted Jun 24, 2003·10 cites·15 claims
- 3566US5915117AComputer architecture for the deferral of exceptions on speculative instructionsINST THE DEV OF EMERGING ARCHI·Filed 1997·Granted Jun 22, 1999·49 cites·34 claims
- 3665US7441107B2Utilizing an advanced load address table for memory disambiguation in an out of order processorINTEL CORP·Filed 2003·Granted Oct 21, 2008·11 cites·21 claims
- 3765US7062636B2Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operationINTEL CORP·Filed 2002·Granted Jun 13, 2006·9 cites·14 claims
- 3865US6148321AProcessor event recognitionINTEL CORP·Filed 1997·Granted Nov 14, 2000·46 cites·17 claims
- 3964US5832260AProcessor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instructionINTEL CORP·Filed 1995·Granted Nov 3, 1998·44 cites·36 claims
- 4063US6216214B1Apparatus and method for a virtual hashed page tableINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Apr 10, 2001·34 cites·17 claims
- 4162US6006325AMethod and apparatus for instruction and data serialization in a computer processorINST THE DEV OF EMERGING ARCHI·Filed 1996·Granted Dec 21, 1999·39 cites·17 claims
- 4260US6584573B1Placing a computer system into a sleeping stateINTEL CORP·Filed 1999·Granted Jun 24, 2003·36 cites·20 claims
- 4353US5895489AMemory management system including an inclusion bit for maintaining cache coherencyINTEL CORP·Filed 1991·Granted Apr 20, 1999·26 cites·6 claims
- 4451US6052801AMethod and apparatus for providing breakpoints on a selectable address rangeINTEL CORP·Filed 1995·Granted Apr 18, 2000·23 cites·22 claims
- 4546US7395415B2Method and apparatus to provide a source operand for an instruction in a processorINTEL CORP·Filed 2004·Granted Jul 1, 2008·0 cites·17 claims
- 4645US2012240116A1Performance In A Virtualization Architecture With A Processor Abstraction LayerLEUNG HIN L·Filed 2012·Application pending·0 cites
- 4745US2005091459A1Flexible mechanism for enforcing coherency among caching structuresFiled 2003·Application pending·0 cites
- 4844US5978900ARenaming numeric and segment registers using common general register poolINTEL CORP·Filed 1996·Granted Nov 2, 1999·18 cites·15 claims
- 4943US8214830B2Performance in a virtualization architecture with a processor abstraction layerLEUNG HIN L·Filed 2005·Granted Jul 3, 2012·0 cites·13 claims
- 5043US6604184B2Virtual memory mapping using region-based page tablesINTEL CORP·Filed 1999·Granted Aug 5, 2003·14 cites·40 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
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