Inventor
CHO NAMJU
KR69 patents
⚠️ This page may combine multiple inventors who share the name “CHO NAMJU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
STATS CHIPPAC LTD
16 patentsUS9362161B2Jun 7, 2016
Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
STATS CHIPPAC LTD47 citations98
US7928552B1Apr 19, 2011
Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
STATS CHIPPAC LTD110 citations98
US8384227B2Feb 26, 2013
Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
STATS CHIPPAC LTD17 citations93
US8349658B2Jan 8, 2013
Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
STATS CHIPPAC LTD19 citations93
US8035235B2Oct 11, 2011
Integrated circuit packaging system with package-on-package and method of manufacture thereof
STATS CHIPPAC LTD21 citations93
US7863735B1Jan 4, 2011
Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof
STATS CHIPPAC LTD38 citations93
US9966335B2May 8, 2018
Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
STATS CHIPPAC LTD4 citations84
US9691707B2Jun 27, 2017
Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
STATS CHIPPAC LTD5 citations84
US9263332B2Feb 16, 2016
Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
STATS CHIPPAC LTD6 citations84
US9064859B2Jun 23, 2015
Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
STATS CHIPPAC LTD8 citations84
US8018034B2Sep 13, 2011
Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
STATS CHIPPAC LTD13 citations84
US9842808B2Dec 12, 2017
Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
STATS CHIPPAC LTD4 citations73
US9269691B2Feb 23, 2016
Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
STATS CHIPPAC LTD3 citations73
US9508635B2Nov 29, 2016
Methods of forming conductive jumper traces
STATS CHIPPAC LTD2 citations63
US8932907B2Jan 13, 2015
Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
STATS CHIPPAC LTD3 citations63
US8350368B2Jan 8, 2013
Semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
STATS CHIPPAC LTD4 citations63
CHI HEEJO
16 patentsUS8288209B1Oct 16, 2012
Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
CHI HEEJO52 citations98
US8143097B2Mar 27, 2012
Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
CHI HEEJO80 citations98
US8138014B2Mar 20, 2012
Method of forming thin profile WLCSP with vertical interconnect over package footprint
CHI HEEJO42 citations98
US9735113B2Aug 15, 2017
Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
CHI HEEJO60 citations97
US9048306B2Jun 2, 2015
Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
CHI HEEJO27 citations93
US8202797B2Jun 19, 2012
Integrated circuit system with recessed through silicon via pads and method of manufacture thereof
CHI HEEJO20 citations93
US9558965B2Jan 31, 2017
Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
CHI HEEJO5 citations84
US9269595B2Feb 23, 2016
Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint
CHI HEEJO11 citations84
US8749040B2Jun 10, 2014
Integrated circuit packaging system with package-on-package and method of manufacture thereof
CHI HEEJO9 citations84
US8716065B2May 6, 2014
Integrated circuit packaging system with encapsulation and method of manufacture thereof
CHI HEEJO17 citations84
US8421203B2Apr 16, 2013
Integrated circuit packaging system with foldable substrate and method of manufacture thereof
CHI HEEJO13 citations84
US8587129B2Nov 19, 2013
Integrated circuit packaging system with through silicon via base and method of manufacture thereof
CHI HEEJO8 citations83
US8455300B2Jun 4, 2013
Integrated circuit package system with embedded die superstructure and method of manufacture thereof
CHI HEEJO12 citations83
US9299650B1Mar 29, 2016
Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
CHI HEEJO6 citations73
US8624370B2Jan 7, 2014
Integrated circuit packaging system with an interposer and method of manufacture thereof
CHI HEEJO6 citations73
US8492888B2Jul 23, 2013
Integrated circuit packaging system with stiffener and method of manufacture thereof
CHI HEEJO5 citations73
CHO NAMJU
9 patentsUS8264091B2Sep 11, 2012
Integrated circuit packaging system with encapsulated via and method of manufacture thereof
CHO NAMJU95 citations98
US9496152B2Nov 15, 2016
Carrier system with multi-tier conductive posts and method of manufacture thereof
CHO NAMJU42 citations94
US8390108B2Mar 5, 2013
Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
CHO NAMJU47 citations94
US8318539B2Nov 27, 2012
Method of manufacture of integrated circuit packaging system with multi-tier conductive interconnects
CHO NAMJU37 citations92
US8476111B2Jul 2, 2013
Integrated circuit packaging system with intra substrate die and method of manufacture thereof
CHO NAMJU8 citations84
US9355939B2May 31, 2016
Integrated circuit package stacking system with shielding and method of manufacture thereof
CHO NAMJU3 citations73
US8564125B2Oct 22, 2013
Integrated circuit packaging system with embedded thermal heat shield and method of manufacture thereof
CHO NAMJU5 citations73
US8541872B2Sep 24, 2013
Integrated circuit package system with package stacking and method of manufacture thereof
CHO NAMJU6 citations73
US8389329B2Mar 5, 2013
Integrated circuit packaging system with package stacking and method of manufacture thereof
CHO NAMJU4 citations63
STATS CHIPPAC PTE LTD
3 patentsUS10510703B2Dec 17, 2019
Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
STATS CHIPPAC PTE LTD8 citations84
US9748157B1Aug 29, 2017
Integrated circuit packaging system with joint assembly and method of manufacture thereof
STATS CHIPPAC PTE LTD10 citations84
US11735530B2Aug 22, 2023
Semiconductor device and method of integrating RF antenna interposer with semiconductor package
STATS CHIPPAC PTE LTD2 citations71
SAMSUNG ELECTRONICS CO LTD
3 patentsUS9055391B2Jun 9, 2015
Method and apparatus for discovering device in wireless communication network
SAMSUNG ELECTRONICS CO LTD5 citations80
US11297666B2Apr 5, 2022
Electronic device and method for forming Wi-Fi direct group thereof
SAMSUNG ELECTRONICS CO LTD3 citations71
US10674555B2Jun 2, 2020
Electronic device and method for forming Wi-Fi direct group thereof
SAMSUNG ELECTRONICS CO LTD4 citations71
SHIN HANGIL
2 patentsUS9397050B2Jul 19, 2016
Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant
SHIN HANGIL53 citations94
US8318541B2Nov 27, 2012
Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
SHIN HANGIL8 citations84
JANG KI YOUN
1 patentShowing the top 50 of 69 patents by PatentIndex Score.