Inventor

RANADE PUSHKAR

US78 patents

⚠️ This page may combine multiple inventors who share the name “RANADE PUSHKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANADE PUSHKAR

MIE FUJITSU SEMICONDUCTOR LTD

Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same

Buried channel deeply depleted channel transistor

High uniformity screen and epitaxial layers for CMOS devices

Semiconductor structure with improved channel stack and method for fabrication thereof

Transistor with threshold voltage set notch and method of fabrication thereof

Semiconductor structure with multiple transistors having various threshold voltages

Semiconductor devices with dopant migration suppression and method of fabrication thereof

Low power semiconductor transistor structure and method of fabrication thereof

Low power semiconductor transistor structure and method of fabrication thereof

Buried channel deeply depleted channel transistor

Method for fabricating a transistor with reduced junction leakage current

CMOS gate stack structures and processes

INTEL CORP

Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby

Active regions with compatible dielectric layers

Integrated circuit structures having airgaps for backside signal routing or power delivery

Method and apparatus to implement an integrated circuit including both dynamic random-access memory (DRAM) and static random-access memory (SRAM)

Integrated circuit interconnect structures with a metal chalcogenide liner

Embedded dynamic random-access memory (eDRAM) to operate based on data access characteristics

Integrated circuit structures having ultra-high conductivity global routing

Providing orthogonal subarrays in a dynamic random access memory

Performing distributed processing using distributed memory

SUVOLTA INC

Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom

Reducing or eliminating pre-amorphization in transistor manufacture

Deeply depleted MOS transistors having a screening layer and methods thereof

Source/drain extension control for advanced transistors

Source/drain extension control for advanced transistors

Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

SHIFREN LUCIAN

Electronic device with controlled threshold voltage

Advanced transistors with punch through suppression

Low power semiconductor transistor structure and method of fabrication thereof

Semiconductor structure and method of fabrication thereof with mixed metal types

Method for fabricating multiple transistor devices on a substrate with varying threshold voltages

RANADE PUSHKAR

CMOS device with dual-epi channels and self-aligned contacts

Source/drain extension control for advanced transistors

Source/drain extension control for advanced transistors

Active regions with compatible dielectric layers

SCUDDER LANCE

Reducing or eliminating pre-amorphization in transistor manufacture

Semiconductor structure with substitutional boron and method for fabrication thereof

Method for substrate preservation during transistor fabrication

THOMPSON SCOTT E

Transistor having reduced junction leakage and methods of forming thereof

Monitoring and measurement of thin film layers

CMOS structures and processes based on selective thinning

UNIV CALIFORNIA

Dual work function CMOS gate technology based on metal interdiffusion

Dual work function CMOS gate technology based on metal interdiffusion

HOFFMANN THOMAS

CMOS gate stack structures and processes

Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer

IBM

Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures

ARGHAVANI REZA

Transistor with threshold voltage set notch and method of fabrication thereof

WANG LINGQUAN

Semiconductor structure with reduced junction leakage and method of fabrication thereof

GREGORY PAUL E

Semiconductor structure with improved channel stack and method for fabrication thereof