Method for fabricating a transistor with reduced junction leakage current

Abstract

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

What is claimed is: 
     
       1. A method for fabricating a transistor with reduced junction leakage current, comprising:
 forming a layered stack, the layered stack including at least a doped screening layer and an undoped channel layer over the doped screening layer; 
 forming a gate over the undoped channel layer, the gate having an effective gate length; 
 forming a source region on one side of the gate and a drain region on another side of the gate; wherein 
 a depth of the doped screening layer is set a preselected distance below the gate such that the distance is a fraction of the effective gate length of the transistor, a thickness of the doped screening layer is preselected such that a bottom of the doped screening layer is above a bottom of the source region and a bottom of the drain region, the doped screen layer extends laterally to and contacts both the source region and the drain region, and further comprising:
 forming a shallow lightly doped drain region in the undoped channel layer on either side of the gate and extending a defined distance inward from an outer edge of the gate; and 
 forming a deep lightly doped drain region on either side of the gate at a depth of the doped screening layer.