Inventor · disambiguated record
Pushkar Ranade
Also filed as: RANADE PUSHKAR · RANADE PUSHKAR SHARAD
76 granted patents·83 pending applications·780 citations·filing 2002–2024
99Inventor score
Top patents by PatentIndex Score
159 records- 0197US8421162B2Advanced transistors with punch through suppressionSHIFREN LUCIAN·Filed 2010·Granted Apr 16, 2013·30 cites·8 claims
- 0297US6794234B2Dual work function CMOS gate technology based on metal interdiffusionUNIV CALIFORNIA·Filed 2002·Granted Sep 21, 2004·124 cites·15 claims
- 0396US8748986B1Electronic device with controlled threshold voltageSHIFREN LUCIAN·Filed 2012·Granted Jun 10, 2014·25 cites·18 claims
- 0496US7598142B2CMOS device with dual-epi channels and self-aligned contactsRANADE PUSHKAR·Filed 2007·Granted Oct 6, 2009·137 cites·7 claims
- 0596US6982230B2Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structuresIBM·Filed 2002·Granted Jan 3, 2006·112 cites·14 claims
- 0695US7691752B2Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed therebyINTEL CORP·Filed 2007·Granted Apr 6, 2010·45 cites·12 claims
- 0794US8735987B1CMOS gate stack structures and processesHOFFMANN THOMAS·Filed 2012·Granted May 27, 2014·18 cites·18 claims
- 0894US8569156B1Reducing or eliminating pre-amorphization in transistor manufactureSCUDDER LANCE·Filed 2012·Granted Oct 29, 2013·25 cites·18 claims
- 0994US8404551B2Source/drain extension control for advanced transistorsRANADE PUSHKAR·Filed 2010·Granted Mar 26, 2013·17 cites·11 claims
- 1093US9112057B1Semiconductor devices with dopant migration suppression and method of fabrication thereofMIE FUJITSU SEMICONDUCTOR LTD·Filed 2012·Granted Aug 18, 2015·17 cites·19 claims
- 1193US9093550B1Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making sameMIE FUJITSU SEMICONDUCTOR LTD·Filed 2013·Granted Jul 28, 2015·20 cites·9 claims
- 1293US8796048B1Monitoring and measurement of thin film layersTHOMPSON SCOTT E·Filed 2012·Granted Aug 5, 2014·16 cites·19 claims
- 1392US9478571B1Buried channel deeply depleted channel transistorMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Oct 25, 2016·10 cites·9 claims
- 1491US8614128B1CMOS structures and processes based on selective thinningTHOMPSON SCOTT E·Filed 2012·Granted Dec 24, 2013·10 cites·18 claims
- 1591US8563384B2Source/drain extension control for advanced transistorsRANADE PUSHKAR·Filed 2013·Granted Oct 22, 2013·9 cites·20 claims
- 1690US9922977B2Transistor with threshold voltage set notch and method of fabrication thereofMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Mar 20, 2018·6 cites·7 claims
- 1789US9299698B2Semiconductor structure with multiple transistors having various threshold voltagesMIE FUJITSU SEMICONDUCTOR LTD·Filed 2013·Granted Mar 29, 2016·7 cites·9 claims
- 1889US9196727B2High uniformity screen and epitaxial layers for CMOS devicesMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Nov 24, 2015·8 cites·7 claims
- 1989US8629016B1Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayerHOFFMANN THOMAS·Filed 2012·Granted Jan 14, 2014·9 cites·15 claims
- 2088US9496261B2Low power semiconductor transistor structure and method of fabrication thereofMIE FUJITSU SEMICONDUCTOR LTD·Filed 2013·Granted Nov 15, 2016·10 cites·13 claims
- 2188US8877619B1Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefromSUVOLTA INC·Filed 2013·Granted Nov 4, 2014·12 cites·5 claims
- 2286US9111785B2Semiconductor structure with improved channel stack and method for fabrication thereofMIE FUJITSU SEMICONDUCTOR LTD·Filed 2013·Granted Aug 18, 2015·7 cites·12 claims
- 2386US8569128B2Semiconductor structure and method of fabrication thereof with mixed metal typesSHIFREN LUCIAN·Filed 2010·Granted Oct 29, 2013·8 cites·10 claims
- 2484US8530286B2Low power semiconductor transistor structure and method of fabrication thereofSHIFREN LUCIAN·Filed 2010·Granted Sep 10, 2013·6 cites·19 claims
- 2583US9646822B2Active regions with compatible dielectric layersRANADE PUSHKAR·Filed 2016·Granted May 9, 2017·2 cites·20 claims
- 2683US9368624B2Method for fabricating a transistor with reduced junction leakage currentMIE FUJITSU SEMICONDUCTOR LTD·Filed 2015·Granted Jun 14, 2016·3 cites·1 claims
- 2783US8937005B2Reducing or eliminating pre-amorphization in transistor manufactureSUVOLTA INC·Filed 2013·Granted Jan 20, 2015·4 cites·20 claims
- 2883US8883600B1Transistor having reduced junction leakage and methods of forming thereofTHOMPSON SCOTT E·Filed 2012·Granted Nov 11, 2014·5 cites·13 claims
- 2981US9041126B2Deeply depleted MOS transistors having a screening layer and methods thereofSUVOLTA INC·Filed 2013·Granted May 26, 2015·6 cites·19 claims
- 3080US9786703B2Buried channel deeply depleted channel transistorMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Oct 10, 2017·2 cites·7 claims
- 3180US7141858B2Dual work function CMOS gate technology based on metal interdiffusionUNIV CALIFORNIA·Filed 2004·Granted Nov 28, 2006·22 cites·6 claims
- 3279US9865596B2Low power semiconductor transistor structure and method of fabrication thereofMIE FUJITSU SEMICONDUCTOR LTD·Filed 2016·Granted Jan 9, 2018·2 cites·14 claims
- 3379US8999861B1Semiconductor structure with substitutional boron and method for fabrication thereofSCUDDER LANCE·Filed 2012·Granted Apr 7, 2015·5 cites·6 claims
- 3479US8759872B2Transistor with threshold voltage set notch and method of fabrication thereofARGHAVANI REZA·Filed 2010·Granted Jun 24, 2014·6 cites·9 claims
- 3579US8686511B2Source/drain extension control for advanced transistorsSUVOLTA INC·Filed 2013·Granted Apr 1, 2014·3 cites·20 claims
- 3677US9847420B2Active regions with compatible dielectric layersINTEL CORP·Filed 2017·Granted Dec 19, 2017·1 cites·20 claims
- 3776US8778786B1Method for substrate preservation during transistor fabricationSCUDDER LANCE·Filed 2012·Granted Jul 15, 2014·4 cites·19 claims
- 3876US8653604B1Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayerSUVOLTA INC·Filed 2012·Granted Feb 18, 2014·3 cites·24 claims
- 3976US8637955B1Semiconductor structure with reduced junction leakage and method of fabrication thereofWANG LINGQUAN·Filed 2012·Granted Jan 28, 2014·5 cites·20 claims
- 4076US8525271B2Semiconductor structure with improved channel stack and method for fabrication thereofGREGORY PAUL E·Filed 2011·Granted Sep 3, 2013·5 cites·8 claims
- 4173US12471362B2Integrated circuit structures having ultra-high conductivity global routingINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·20 claims
- 4273US9006843B2Source/drain extension control for advanced transistorsSUVOLTA INC·Filed 2014·Granted Apr 14, 2015·2 cites·20 claims
- 4371US9406567B1Method for fabricating multiple transistor devices on a substrate with varying threshold voltagesSHIFREN LUCIAN·Filed 2012·Granted Aug 2, 2016·3 cites·12 claims
- 4471US7861406B2Method of forming CMOS transistors with dual-metal silicide formed through the contact openingsINTEL CORP·Filed 2007·Granted Jan 4, 2011·5 cites·7 claims
- 4567US9391076B1CMOS structures and processes based on selective thinningMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Jul 12, 2016·1 cites·7 claims
- 4665US9281248B1CMOS gate stack structures and processesMIE FUJITSU SEMICONDUCTOR LTD·Filed 2014·Granted Mar 8, 2016·1 cites·25 claims
- 4765US2025358993A1Multi-gate negative differential impedance device for sramINTEL CORP·Filed 2024·Application pending·0 cites
- 4864US12498876B2Performing distributed processing using distributed memoryINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 4964US8394687B2Ultra-abrupt semiconductor junction profileRANADE PUSHKAR·Filed 2007·Granted Mar 12, 2013·2 cites·9 claims
- 5062US10217838B2Semiconductor structure with multiple transistors having various threshold voltagesMIE FUJITSU SEMICONDUCTOR LTD·Filed 2018·Granted Feb 26, 2019·0 cites·9 claims
Showing the top 50 of 159 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →