Inventor

LEE TSUNG-LIN

TW138 patents

⚠️ This page may combine multiple inventors who share the name “LEE TSUNG-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE TSUNG-LIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Structure and formation method of semiconductor device structure with nanowires

Method for fabricating a strained structure and structure formed

Gate spacer structure and method of forming same

Gate spacer structure and method of forming same

Fin field effect transistor (FinFET) device structure with dummy fin structure and method for forming the same

Method of manufacturing a semiconductor device with multilayered channel structure

Structure and formation method of semiconductor device with channel layer

FINFET structures and methods of forming the same

Strain enhancement for FinFETs

Structure and formation method of semiconductor device structure with nanowires

Air spacer for a gate structure of a transistor

FinFET structure and method with reduced fin buckling

FinFET structure and method with reduced fin buckling

Method of manufacturing a semiconductor device with multilayered channel structure

Different isolation liners for different type FinFETs and associated isolation feature fabrication

Structure and formation method of semiconductor device structure with nanowires

TAIWAN SEMICONDUCTOR MFG

FinFETs with multiple Fin heights

Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory

Method for fabricating a strained structure

FinFETs with multiple fin heights

FinFETs with multiple fin heights

Structure and method for a sidewall SONOS memory device

FinFETs with different fin height and EPI height setting

Voids in STI regions for forming bulk FinFETs

FinFETs with different fin height and EPI height setting

Multi-fin device by self-aligned castle fin formation

Forming inter-device STI regions and intra-device STI regions using different dielectric materials

Integrated circuit with multi recessed shallow trench isolation

Non-uniform semiconductor device active area pattern formation

Voids in STI regions for forming bulk FinFETs

Static noise-immune SRAM cells

LEE TSUNG-LIN

Strained structure of semiconductor device and method of making the strained structure

Gate structure for semiconductor device

Integrated circuit with multi recessed shallow trench isolation

Method for fabricating a strained structure

FinFETs with different fin heights

Integrated circuit structures with multiple FinFETs

Sacrificial offset protection film for a FinFET device

Semiconductor device having a strained region

FinFET design with reduced current crowding

YUAN FENG

STI shape near fin bottom of Si fin in bulk FinFET

Voids in STI regions for forming bulk FinFETs

Forming inter-device STI regions and intra-device STI regions using different dielectric materials

SHIEH MING-FENG

Cross OD FinFET patterning

Cross OD FinFET patterning

SILICON INTEGRATED SYS CORP

Frequency synchronization apparatus and method for OFDM systems

OFDM receiver and metric generator thereof

SUN SEY-PING

Semiconductor device having elevated structure and method of manufacturing the same

CHEN HSIN-CHIH

Multi-fin device by self-aligned castle fin formation

VAN DAL MARK

Strained channel field effect transistor