FinFETs with different fin height and EPI height setting

Abstract

An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

What is claimed is: 
     
       1. A method comprising:
 forming a first and a second plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein a first portion of the semiconductor substrate between the first plurality of STI regions is configured as a first semiconductor strip, and a second portion of the semiconductor substrate between the second plurality of STI regions is configured as a second semiconductor strip; 
 recessing the first semiconductor strip to form a first recess having a first depth; 
 performing a first epitaxy to grow a first epitaxy strip in the first recess; 
 recessing the second semiconductor strip to form a second recess having a second depth different from the first depth; 
 performing a second epitaxy to grow a second epitaxy strip in the second recess; and 
 recessing the first plurality of STI regions and the second plurality of STI regions to form a first semiconductor fin and a second semiconductor fin, respectively, wherein the first semiconductor fin comprises a top portion of the first epitaxy strip, and the second semiconductor fin comprises a top portion of the second epitaxy strip. 
 
     
     
       2. The method of  claim 1 , wherein the recessing the first plurality of STI regions and the second plurality of STI regions comprises etching the first plurality of STI regions and the plurality of STI regions in different etching processes. 
     
     
       3. The method of  claim 2 , wherein the first plurality of STI regions and the second plurality of STI regions are recessed using different etching masks. 
     
     
       4. The method of  claim 1 , wherein the recessing the first plurality of STI regions and the second plurality of STI regions comprises etching the first plurality of STI regions and the second plurality of STI regions simultaneously. 
     
     
       5. The method of  claim 1 , wherein the recessing the first plurality of STI regions and the second plurality of STI regions comprises:
 recessing the first plurality of STI regions, with top surfaces of remaining portions of the first plurality of STI regions being higher than a bottom surface of the first epitaxy strip; and 
 recessing the second plurality of STI regions, with top surfaces of remaining portions of the second plurality of STI regions being lower than a bottom surface of the second epitaxy strip. 
 
     
     
       6. The method of  claim 5 , wherein the first epitaxy strip has a first bandgap higher than a bandgap of the first semiconductor strip, and the second epitaxy strip has a second bandgap lower than a bandgap of the second semiconductor strip. 
     
     
       7. The method of  claim 5  further comprising:
 forming a first gate dielectric and a first gate electrode on a top surface and sidewalls of the first semiconductor fin; and 
 forming a second gate dielectric and a second gate electrode on a top surface and sidewalls of the second semiconductor fin. 
 
     
     
       8. The method of  claim 1  further comprising performing planarization steps to level a top surface of the first epitaxy strip with a top surface of the second epitaxy strip. 
     
     
       9. A method comprising:
 forming a first and a second plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein a first portion of the semiconductor substrate between the first plurality of STI regions is configured as a first semiconductor strip, and a second portion of the semiconductor substrate between the second plurality of STI regions is configured as a second semiconductor strip; 
 recessing the first semiconductor strip to form a first recess having a first depth; 
 performing a first epitaxy to grow a first epitaxy strip in the first recess; 
 recessing the second semiconductor strip to form a second recess; 
 performing a second epitaxy to grow a second epitaxy strip in the second recess; 
 recessing the first plurality of STI regions, with top surfaces of remaining portions of the first plurality of STI regions being higher than a bottom surface of the first epitaxy strip; and 
 recessing the second plurality of STI regions, with top surfaces of remaining portions of the second plurality of STI regions being lower than a bottom surface of the second epitaxy strip. 
 
     
     
       10. The method of  claim 9 , wherein a top portion of the first epitaxy strip forms a first semiconductor fin, and an entirety of the second epitaxy strip and a top portion of the second semiconductor strip forms a second semiconductor fin, and the method further comprises:
 forming a first gate dielectric and a first gate electrode on a top surface and a sidewall of the first semiconductor fin; and 
 forming a second gate dielectric and a second gate electrode on a top surface and a sidewall of the second semiconductor fin. 
 
     
     
       11. The method of  claim 9 , wherein the recessing the first plurality of STI regions and the recessing the second plurality of STI regions are performed in different etching processes. 
     
     
       12. The method of  claim 9 , wherein the top surfaces of remaining portions of the first plurality of STI regions are higher than the top surfaces of remaining portions of the second plurality of STI regions. 
     
     
       13. The method of  claim 9 , wherein the first epitaxy strip has a first bandgap greater than a bandgap of the semiconductor substrate, and the second epitaxy strip has a second bandgap smaller than the bandgap of the semiconductor substrate, and the first recess is deeper than the second recess. 
     
     
       14. The method of  claim 9 , wherein the recessing the first plurality of STI regions and the second plurality of STI regions comprises etching the first plurality of STI regions and the plurality of STI regions simultaneously. 
     
     
       15. The method of  claim 9  further comprising performing planarization steps to level a top surface of the first epitaxy strip with a top surface of the second epitaxy strip. 
     
     
       16. A method comprising:
 forming a first and a second plurality of shallow trench isolation (STI) regions in a semiconductor substrate, wherein a first portion of the semiconductor substrate between the first plurality of STI regions is configured as a first semiconductor strip, and a second portion of the semiconductor substrate between the second plurality of STI regions is configured as a second semiconductor strip; 
 recessing the first semiconductor strip to form a first recess having a first depth; 
 performing a first epitaxy to grow a first epitaxy strip in the first recess; 
 recessing the second semiconductor strip to form a second recess having a second depth; 
 performing a second epitaxy to grow a second epitaxy strip in the second recess; 
 recessing the first plurality of STI regions, with first top surfaces of remaining portions of the first plurality of STI regions being higher than a bottom surface of the first epitaxy strip; and 
 recessing the second plurality of STI regions, with second top surfaces of remaining portions of the second plurality of STI regions being lower than a bottom surface of the second epitaxy strip, and the second top surfaces are higher than the first top surfaces. 
 
     
     
       17. The method of  claim 16 , wherein the first epitaxy strip has a first bandgap greater than a bandgap of the semiconductor substrate, and the second epitaxy strip has a second bandgap smaller than the bandgap of the semiconductor substrate. 
     
     
       18. The method of  claim 16  further comprising:
 forming a first gate dielectric and a first gate electrode on a top surface and sidewalls of the first epitaxy strip; and 
 forming a second gate dielectric and a second gate electrode on a top surface and sidewalls of the second epitaxy strip. 
 
     
     
       19. The method of  claim 16  further comprising performing planarization steps to level a top surface of the first epitaxy strip with a top surface of the second epitaxy strip. 
     
     
       20. The method of  claim 16 , wherein the first epitaxy strip and the second epitaxy strip are formed of different materials.