Structure and method for a sidewall SONOS memory device

Abstract

A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.

1. A method of manufacturing a semiconductor device, comprising:
 forming a gate stack on a substrate, the gate stack having a sidewall; 
 depositing an oxide-nitride-oxide material on the gate stack; 
 removing portions of the oxide-nitride-oxide material to form an oxide-nitride-oxide structure having a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate; 
 depositing a top oxide material over the substrate; 
 depositing a silicon nitride spacer material over the top oxide material; 
 removing portions of the top oxide material and the silicon nitride spacer material to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material; 
 forming source/drain regions in the substrate; and 
 wherein a portion of a top of the oxide-nitride-oxide structure is recessed relative to a top of the gate stack. 
 
   
   
     2. The method of  claim 1 , wherein a top of the oxide-nitride-oxide structure is recessed relative to a top of the nitride spacer. 
   
   
     3. The method of  claim 1 , further comprising forming lightly doped drain regions in the substrate adjacent the oxide-nitride-oxide structure. 
   
   
     4. The method of  claim 1 , wherein the gate stack comprises a gate electrode and a gate dielectric, and the gate dielectric comprises a high-K dielectric material deposited by a chemical vapor deposition process. 
   
   
     5. The method of  claim 1 , wherein a nitride material in the oxide-nitride-oxide structure is a high-K dielectric material deposited by a chemical vapor deposition process. 
   
   
     6. The method of  claim 1 , wherein a top oxide in the oxide-nitride-oxide structure comprises a multi-layer material deposited by a chemical vapor deposition process. 
   
   
     7. The method of  claim 1 , wherein a thickness of a nitride material in the oxide-nitride-oxide structure is controlled by a chemical vapor deposition process. 
   
   
     8. The method of  claim 1 , wherein a thickness of a nitride material in the oxide-nitride-oxide structure extending along the substrate is controlled by a dry etch process. 
   
   
     9. A method of manufacturing a semiconductor device, comprising:
 forming a gate stack on a substrate, the gate stack having a sidewall; 
 forming a recess in a lower portion of the sidewall; 
 depositing an oxide-nitride-oxide material on the gate stack; 
 removing portions of the oxide-nitride-oxide material to form an oxide-nitride-oxide structure having a generally L-shaped cross-section, wherein the oxide-nitride-oxide structure is conformably formed in the recessed portion of the sidewall, a vertical portion of the oxide-nitride-oxide structure is formed along at least part of the gate stack sidewall and a horizontal portion along the substrate; 
 depositing a top oxide material over the substrate; 
 depositing a silicon nitride spacer material over the top oxide material; 
 removing portions of the top oxide material and the silicon nitride spacer material to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material; and 
 forming source/drain regions in the substrate. 
 
   
   
     10. The method of  claim 9 , further comprising forming lightly doped drain regions in the substrate adjacent the oxide-nitride-oxide structure. 
   
   
     11. The method of  claim 9 , wherein the gate stack comprises a high-K dielectric material deposited by a chemical vapor deposition process. 
   
   
     12. The method of  claim 9 , wherein a nitride material in the oxide-nitride-oxide structure is deposited by a chemical vapor deposition process. 
   
   
     13. The method of  claim 9 , wherein a top oxide in the oxide-nitride-oxide structure comprises a multi-layer material deposited by a chemical vapor deposition process. 
   
   
     14. The method of  claim 9 , wherein a thickness of a nitride material in the oxide-nitride-oxide structure extending along the gate stack and is controlled by a chemical vapor deposition process. 
   
   
     15. The method of  claim 9 , wherein a nitride material in the oxide-nitride-oxide structure extending along the substrate is controlled by a dry etch process. 
   
   
     16. A method of manufacturing a semiconductor device, comprising:
 forming a gate stack on a substrate, the gate stack having a sidewall; 
 forming a substrate recess adjacent the gate stack; 
 depositing an oxide-nitride-oxide material over the substrate; 
 removing portions of the oxide-nitride-oxide material to form an oxide-nitride-oxide structure having a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate; 
 depositing a top oxide material over the substrate; 
 depositing a silicon nitride spacer material over the top oxide material; 
 removing portions of the top oxide material and the silicon nitride spacer material to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material; and 
 forming source/drain regions in the substrate. 
 
   
   
     17. The method of  claim 16 , further comprising forming lightly doped drain regions in the substrate adjacent the oxide-nitride-oxide structure. 
   
   
     18. The method of  claim 16 , wherein a gate dielectric comprises a high-K dielectric material deposited by a chemical vapor deposition process, wherein a nitride material in the oxide-nitride-oxide structure is a high-K dielectric material deposited by a chemical vapor deposition process, and wherein the top oxide material in the oxide-nitride-oxide structure comprises a multi-layer material deposited by a chemical vapor deposition process. 
   
   
     19. The method of  claim 16 , wherein a thickness of a nitride material in the oxide-nitride-oxide structure extending along the gate stack is controlled by a chemical vapor deposition process. 
   
   
     20. The method of  claim 16 , wherein a nitride material in the oxide-nitride-oxide structure extending along the substrate is controlled by a dry etch process.