Structure and formation method of semiconductor device structure with nanowires

Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

What is claimed is: 
     
       1. A semiconductor device structure, comprising:
 a plurality of nanostructures over a substrate; 
 a gate electrode surrounding the nanostructures; 
 a source/drain portion adjacent to the gate electrode; 
 a semiconductor layer between the gate electrode and the source/drain portion, wherein the semiconductor layer comprises silicon germanium (SiGe); 
 a spacer element formed on a sidewall of the gate electrode, wherein the spacer element is separated from the semiconductor layer, wherein a topmost nanostructure is higher than a topmost surface of the semiconductor layer; 
 an interlayer dielectric layer formed over the source/drain portion; 
 an etch stop layer between the source/drain portion and the interlayer dielectric layer; and 
 a protective element formed over the interlayer dielectric layer. 
 
     
     
       2. The semiconductor device structure as claimed in  claim 1 , further comprising:
 a protective layer adjacent to the semiconductor layer, wherein the protective layer comprises a semiconductor material. 
 
     
     
       3. The semiconductor device structure as claimed in  claim 1 , wherein the spacer element and the semiconductor layer are made of different materials. 
     
     
       4. The semiconductor device structure as claimed in  claim 1 , wherein the semiconductor layer has a curved surface facing the gate electrode. 
     
     
       5. The semiconductor device structure as claimed in  claim 1  , wherein a top surface of the protective element is leveled with a top surface of the gate electrode. 
     
     
       6. The semiconductor device structure as claimed in  claim 1 , wherein a top surface of the source/drain portion is higher than a topmost surface of the nanostructures. 
     
     
       7. The semiconductor device structure as claimed in  claim 1 , further comprising:
 a high-k dielectric layer adjacent to the semiconductor layer, wherein the high-K dielectric layer is between the gate electrode and the semiconductor layer. 
 
     
     
       8. The semiconductor device structure as claimed in  claim 1 , wherein a width of the spacer element is greater than a width of the semiconductor layer. 
     
     
       9. The semiconductor device structure as claimed in  claim 1 , wherein a top surface of the source/drain portion is higher than a bottom surface of the spacer element. 
     
     
       10. A semiconductor device structure, comprising:
 a plurality of nanostructures over a substrate; 
 a gate electrode surrounding the nanostructures; 
 a source/drain portion adjacent to the gate electrode; 
 a semiconductor layer between the gate electrode and the source/drain portion; and 
 a protective layer adjacent to the semiconductor layer, wherein the protective layer is between a spacer and the gate electrode, wherein the protective layer comprises silicon germanium (SiGe), and top surfaces and bottom surfaces of the nanostructures are in direct contact with the protective layer, wherein a topmost surface of the protective layer is higher than a bottom surface of the spacer. 
 
     
     
       11. The semiconductor device structure as claimed in  claim 10 , wherein the protective layer has a curved surface facing the gate electrode. 
     
     
       12. The semiconductor device structure as claimed in  claim 10 , further comprising:
 an interlayer dielectric layer formed over the source/drain portion; and 
 a protective element formed over the interlayer dielectric layer. 
 
     
     
       13. The semiconductor device structure as claimed in  claim 10 , wherein a top surface of the source/drain portion is higher than a topmost surface of the nanostructures. 
     
     
       14. The semiconductor device structure as claimed in  claim 10 , further comprising:
 a dielectric layer between the protective layer and the gate electrode, wherein the dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. 
 
     
     
       15. The semiconductor device structure as claimed in  claim 10 , further comprising:
 a spacer element formed adjacent to the gate electrode, wherein a width of the spacer element is greater than a width of the semiconductor layer. 
 
     
     
       16. A semiconductor device structure, comprising:
 a plurality of nanostructures over a substrate; 
 a high-k dielectric layer surrounding the nanostructures; 
 a gate electrode surrounding the high-k dielectric layer; 
 a source/drain portion adjacent to the gate electrode; 
 a protective layer between the source/drain portion and the gate electrode, wherein the protective layer comprises a semiconductor material and is under the high-k dielectric layer; and 
 a dielectric layer between the protective layer and the high-k dielectric layer, wherein the dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. 
 
     
     
       17. The semiconductor device structure as claimed in  claim 16 , further comprising:
 a semiconductor layer between the protective layer and the source/drain portion. 
 
     
     
       18. The semiconductor device structure as claimed in  claim 17 , wherein the semiconductor layer comprises silicon (Si) or silicon germanium (SiGe). 
     
     
       19. The semiconductor device structure as claimed in  claim 17 , further comprising:
 a spacer element formed adjacent to the gate electrode, wherein a width of the spacer element is greater than a width of the semiconductor layer. 
 
     
     
       20. The semiconductor device structure as claimed in  claim 16 , wherein the protective layer has a curved surface facing the gate electrode.