Inventor · disambiguated record
Chim Seng Seet
Also filed as: SEET CHIM SENG
28 granted patents·11 pending applications·82 citations·filing 2000–2023
95Inventor score
Files withGLOBALFOUNDRIES SG PTE LTD29CHARTERED SEMICONDUCTOR MFG4LIU HUANG2RAO XUESONG2CHARTERED SEMICONDUCTOR MFG CO1
Top patents by PatentIndex Score
39 records- 0191US10008387B1Embedded memory in back-end-of-line low-k dielectricGLOBALFOUNDRIES SG PTE LTD·Filed 2017·Granted Jun 26, 2018·8 cites·20 claims
- 0291US9997562B1Mram memory device and manufacturing method thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2017·Granted Jun 12, 2018·9 cites·20 claims
- 0385US10128309B2Storage layer for magnetic memory with high thermal stabilityGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Nov 13, 2018·4 cites·20 claims
- 0485US7790617B2Formation of metal silicide layer over copper interconnect for reliability enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Sep 7, 2010·11 cites·29 claims
- 0583US10468171B1Integrated circuits with magnetic tunnel junctions and methods of producing the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Nov 5, 2019·2 cites·17 claims
- 0682US7253097B2Integrated circuit system using dual damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 7, 2007·11 cites·20 claims
- 0778US10483121B2Embedded memory in back-end-of-line low-k dielectricGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Nov 19, 2019·2 cites·6 claims
- 0876US7803704B2Reliable interconnectsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Sep 28, 2010·6 cites·20 claims
- 0975US8102054B2Reliable interconnectsZHANG BEI CHAO·Filed 2010·Granted Jan 24, 2012·5 cites·20 claims
- 1073US8354347B2Method of forming high-k dielectric stop layer for contact hole openingGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Jan 15, 2013·6 cites·29 claims
- 1168US12284925B2Memory device having a switching element thicker at a first side than at a second side and method of forming the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2023·Granted Apr 22, 2025·0 cites·18 claims
- 1268US9972774B2Magnetic memory with high thermal budgetGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted May 15, 2018·1 cites·19 claims
- 1364US6403478B1Low pre-heat pressure CVD TiN processCHARTERED SEMICONDUCTOR MFG CO·Filed 2000·Granted Jun 11, 2002·11 cites·20 claims
- 1463US12224089B2Thin film resistorGLOBALFOUNDRIES SG PTE LTD·Filed 2022·Granted Feb 11, 2025·0 cites·19 claims
- 1562US10840297B2Storage layer for magnetic memory with high thermal stabilityGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Nov 17, 2020·1 cites·10 claims
- 1658US9859236B2Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers thereon and methods for fabricating sameGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Jan 2, 2018·1 cites·20 claims
- 1754US9293388B2Reliable passivation layers for semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Mar 22, 2016·1 cites·20 claims
- 1853US11164858B2Integrated circuits and methods of forming integrated circuitsGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted Nov 2, 2021·0 cites·20 claims
- 1949US2021057645A1Memory device and method of forming the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Application pending·0 cites
- 2048US9842989B2Magnetic memory with high thermal budgetGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Dec 12, 2017·0 cites·20 claims
- 2145US10707358B2Selective shielding of ambient light at chip levelGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Jul 7, 2020·0 cites·12 claims
- 2245US9548371B2Integrated circuits having nickel silicide contacts and methods for fabricating the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Jan 17, 2017·0 cites·20 claims
- 2344US10297745B2Composite spacer layer for magnetoresistive memoryGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted May 21, 2019·0 cites·20 claims
- 2444US7294241B2Method to form alpha phase Ta and its application to IC manufacturingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Nov 13, 2007·3 cites·26 claims
- 2543US2019304521A1Magnetic random access memory structures, integrated circuits, and methods for fabricating the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Application pending·0 cites
- 2640US9023725B2Filament free silicide formationGLOBALFOUNDRIES SG PTE LTD·Filed 2012·Granted May 5, 2015·0 cites·15 claims
- 2740US8492236B1Step-like spacer profileRAO XUESONG·Filed 2012·Granted Jul 23, 2013·0 cites·20 claims
- 2840US2021013405A1Resistive switching nonvolatile random access memory deviceGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Application pending·0 cites
- 2939US11751483B2Spin diode devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted Sep 5, 2023·0 cites·20 claims
- 3039US2021028349A1Integrated circuits with magnetic tunnel junction memory cells and methods for producing the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Application pending·0 cites
- 3138US2018175284A1Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (mtj) structuresGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 3237US2014117545A1Copper hillock prevention with hydrogen plasma treatment in a dedicated chamberLIU HUANG·Filed 2012·Application pending·0 cites
- 3337US2016181197A1Reliable passivation layers for semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 3437US2021159393A1Magnetic tunnel junction devices and methods of forming thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Application pending·0 cites
- 3536US8828858B2Spacer profile engineering using films with continuously increased etch rate from inner to outer surfaceRAO XUESONG·Filed 2012·Granted Sep 9, 2014·0 cites·11 claims
- 3636US2016276580A1Bottom electrode for magnetic memory to increase tmr and thermal budgetGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 3736US2018233661A1Device alignment mark using a planarization processGLOBALFOUNDRIES SG PTE LTD·Filed 2017·Application pending·0 cites
- 3834US10475495B2Integrated circuits with magnetic tunnel junctions and methods of producing the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Nov 12, 2019·0 cites·9 claims
- 3934US2012273949A1Method of forming oxide encapsulated conductive featuresLIU HUANG·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →