Spacer profile engineering using films with continuously increased etch rate from inner to outer surface

Abstract

Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.

What is claimed is: 
     
       1. A method comprising:
 forming a gate electrode on a substrate; 
 forming a spacer layer over the gate electrode and substrate having a first surface nearest the gate electrode and substrate and a second surface furthest from the gate electrode and substrate, by depositing a spacer material using ozone (O 3 ) and tetraethyl orthosilicate (TEOS) as precursors and continuously increasing the TEOS while maintaining a constant flow of O 3  or by depositing a spacer material comprising carbon and causing a gradient of carbon content in the spacer layer by causing carbon depletion at the second surface of the spacer layer, the continuously increasing TEOS or gradient of carbon content causing a continuously increasing etch rate from the first surface to the second surface; and 
 etching the spacer layer to form a tapered spacer on each side of the gate electrode. 
 
     
     
       2. The method according to  claim 1 , comprising forming the spacer layer by:
 continuously decreasing the density of the spacer material during deposition. 
 
     
     
       3. The method according to  claim 1 , comprising depostiting the spacer material using silane (SiH 4 ) and carbon dioxide (CO 2 ) as a precursor. 
     
     
       4. The method according to  claim 1 , comprising causing carbon depletion by performing an O 2  or O 3  plasma treatment after deposition of the spacer material. 
     
     
       5. The method according to  claim 2 , comprising continuously decreasing the density of the spacer material by continuously decreasing an O 3  to TEOS ratio during deposition of the spacer material. 
     
     
       6. The method according to  claim 5 , comprising continuously decreasing the O 3  to TEOS ratio by continuously increasing the TEOS from 1.125 grams (g) to 2.7 g while maintaining a constant flow of O 3 . 
     
     
       7. The method according to  claim 3 , further comprising tuning the carbon content in a range of 0-5% by controlling a flow of the SiH 4  and the CO 2 . 
     
     
       8. A method comprising:
 forming at least two gate electrodes on a substrate; 
 forming a spacer layer over the gate electrodes and substrate having a first surface nearest the gate electrodes and substrate and a second surface furthest from the gate electrodes and substrate, by depositing a spacer material using ozone (O 3 ) and tetraethyl orthosilicate (TEOS) as precursors and continuously increasing the TEOS while maintaining a constant flow of O 3  or by depositing a spacer material comprising carbon and causing a decreasing gradient of carbon content in the spacer layer by causing carbon depletion at the second surface of the spacer layer, the continuously increasing TEOS or decreasing gradient of carbon content causing a continuously increasing etch rate from the first surface to the second surface; 
 etching the spacer layer to form a tapered spacer on each side of each gate electrode; and depositing an interlayer dielectric (ILD) on and between the at least two gate electrodes. 
 
     
     
       9. The method according to  claim 8 , comprising etching the spacer layer by anisotropic reactive ion etching (RIE). 
     
     
       10. The method according to  claim 9 , comprising continuously decreasing the O 3  to TEOS ratio by continuously increasing the TEOS from 1.125 grams (g) to 2.7 g while maintaining a constant flow of O 3 . 
     
     
       11. The method according to  claim 9 , comprising forming the spacer layer by: depositing a nitrogen-free dielectric antireflective coating using silane (SiH 4 ) and carbon dioxide (CO 2 ) as precursors; and performing an O 2  or O 3  plasma treatment after deposition of the dielectric antireflective coating to cause the depletion of carbon content from the first surface to the second surface of the spacer layer.