Inventor · disambiguated record
Cheemen Yu
Also filed as: YU CHEEMEN
32 granted patents·15 pending applications·183 citations·filing 2005–2013
96Inventor score
Top patents by PatentIndex Score
47 records- 0195US7550834B2Stacked, interconnected semiconductor packagesSANDISK CORP·Filed 2006·Granted Jun 23, 2009·38 cites·15 claims
- 0292US7375415B2Die package with asymmetric leadframe connectionSANDISK CORP·Filed 2005·Granted May 20, 2008·23 cites·30 claims
- 0387US7538438B2Substrate warpage control and continuous electrical enhancementSANDISK CORP·Filed 2005·Granted May 26, 2009·15 cites·36 claims
- 0485US7746661B2Printed circuit board with coextensive electrical connectors and contact pad areasSANDISK CORP·Filed 2006·Granted Jun 29, 2010·8 cites·18 claims
- 0585US7355283B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK CORP·Filed 2005·Granted Apr 8, 2008·10 cites·12 claims
- 0683US7772686B2Memory card fabricated using SiP/SMT hybrid technologySANDISK CORP·Filed 2007·Granted Aug 10, 2010·13 cites·28 claims
- 0783US7728411B2COL-TSOP with nonconductive material for reducing package capacitanceSANDISK CORP·Filed 2006·Granted Jun 1, 2010·12 cites·21 claims
- 0882US7615409B2Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packagesSANDISK CORP·Filed 2006·Granted Nov 10, 2009·8 cites·10 claims
- 0977US8395246B2Two-sided die in a four-sided leadframe based packageYU CHEEMEN·Filed 2007·Granted Mar 12, 2013·8 cites·19 claims
- 1076US8097495B2Die package with asymmetric leadframe connectionLEE MING HSUN·Filed 2008·Granted Jan 17, 2012·7 cites·15 claims
- 1172US8487441B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingCHIU CHIN-TIEN·Filed 2007·Granted Jul 16, 2013·4 cites·11 claims
- 1272US7806731B2Rounded contact fingers on substrate/PCB for crack preventionSANDISK CORP·Filed 2005·Granted Oct 5, 2010·5 cites·38 claims
- 1371US8470640B2Method of fabricating stacked semiconductor package with localized cavities for wire bondingTAKIAR HEM·Filed 2008·Granted Jun 25, 2013·5 cites·15 claims
- 1469US7763980B2Semiconductor die having a distribution layerSANDISK CORP·Filed 2007·Granted Jul 27, 2010·3 cites·10 claims
- 1569US7611927B2Method of minimizing kerf width on a semiconductor substrate panelSANDISK CORP·Filed 2007·Granted Nov 3, 2009·4 cites·27 claims
- 1668US7967184B2Padless substrate for surface mounted componentsSANDISK CORP·Filed 2005·Granted Jun 28, 2011·4 cites·6 claims
- 1766US7435624B2Method of reducing mechanical stress on a semiconductor die during fabricationSANDISK CORP·Filed 2006·Granted Oct 14, 2008·4 cites·15 claims
- 1865US7615861B2Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cardsSANDISK CORP·Filed 2006·Granted Nov 10, 2009·2 cites·9 claims
- 1963US7663216B2High density three dimensional semiconductor die packageSANDISK CORP·Filed 2005·Granted Feb 16, 2010·2 cites·26 claims
- 2062US8294251B2Stacked semiconductor package with localized cavities for wire bondingTAKIAR HEM·Filed 2008·Granted Oct 23, 2012·2 cites·20 claims
- 2162US7952179B2Semiconductor package having through holes for molding back side of packageSANDISK CORP·Filed 2007·Granted May 31, 2011·2 cites·16 claims
- 2261US7772047B2Method of fabricating a semiconductor die having a redistribution layerSANDISK CORP·Filed 2007·Granted Aug 10, 2010·2 cites·34 claims
- 2360US7592699B2Hidden plating tracesSANDISK CORP·Filed 2005·Granted Sep 22, 2009·1 cites·18 claims
- 2458US7939382B2Method of fabricating a semiconductor package having through holes for molding back side of packageSANDISK CORP·Filed 2007·Granted May 10, 2011·1 cites·30 claims
- 2557US9006912B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2012·Granted Apr 14, 2015·0 cites·14 claims
- 2651US8728864B2Method of fabricating a memory card using SIP/SMT hybrid technologySANDISK TECHNOLOGIES INC·Filed 2012·Granted May 20, 2014·0 cites·6 claims
- 2750US2013200507A1Two-sided die in a four-sided leadframe based packageSANDISK TECHNOLOGIES INC·Filed 2013·Application pending·0 cites
- 2848US2007262434A1Interconnected ic packages with vertical smt padsSANDISK CORP·Filed 2007·Application pending·0 cites
- 2947US8058099B2Method of fabricating a two-sided die in a four-sided leadframe based packageYU CHEEMEN·Filed 2007·Granted Nov 15, 2011·0 cites·17 claims
- 3046US7772107B2Methods of forming a single layer substrate for high capacity memory cardsSANDISK CORP·Filed 2006·Granted Aug 10, 2010·0 cites·17 claims
- 3144US8637972B2Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panelLIAO CHIH-CHIN·Filed 2007·Granted Jan 28, 2014·0 cites·30 claims
- 3244US8212360B2Semiconductor die having a redistribution layerLIAO CHIEN-KO·Filed 2011·Granted Jul 3, 2012·0 cites·15 claims
- 3344US2007158799A1Interconnected IC packages with vertical SMT padsCHIU CHIN-TIEN·Filed 2005·Application pending·0 cites
- 3443US8318535B2Method of fabricating a memory card using SiP/SMT hybrid technologyYE NING·Filed 2007·Granted Nov 27, 2012·0 cites·19 claims
- 3542US2009085231A1Method of reducing memory card edge roughness by particle blastingCHIU CHIN-TIEN·Filed 2007·Application pending·0 cites
- 3642US2008305306A1Semiconductor molded panel having reduced warpageYU CHEEMEN·Filed 2007·Application pending·0 cites
- 3742US2008305576A1Method of reducing warpage in semiconductor molded panelYU CHEEMEN·Filed 2007·Application pending·0 cites
- 3842US2009065902A1Method of forming a semiconductor die having a sloped edge for receiving an electrical connectorYU CHEEMEN·Filed 2007·Application pending·0 cites
- 3941US2007267759A1Semiconductor device with a distributed plating patternLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 4041US2007235848A1Substrate having conductive traces isolated by laser to allow electrical inspectionLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 4141US2009004783A1Method of package stacking using unbalanced molded tsopLEE MING HSUN·Filed 2007·Application pending·0 cites
- 4241US2007269929A1Method of reducing stress on a semiconductor die with a distributed plating patternLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 4341US2009004774A1Method of multi-chip packaging in a tsop packageLEE MING HSUN·Filed 2007·Application pending·0 cites
- 4441US2009001533A1Multi-chip packaging in a tsop packageLEE MING HSUN·Filed 2007·Application pending·0 cites
- 4541US2009001529A1Package stacking using unbalanced molded tsopLEE MING HSUN·Filed 2007·Application pending·0 cites
- 4640US8878346B2Molded SiP package with reinforced solder columnsCHIU CHIN-TIEN·Filed 2006·Granted Nov 4, 2014·0 cites·24 claims
- 4738US2007096285A1Semiconductor die package including construction for preventing delamination and/or cracking of the semiconductor dieCHIU CHIN-TIEN·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →