Inventor · disambiguated record
Daniel J. Connelly
Also filed as: CONNELLY DANIEL · CONNELLY DANIEL J
53 granted patents·4 pending applications·1,286 citations·filing 2002–2025
99Inventor score
Top patents by PatentIndex Score
57 records- 0199US10593761B1Method for making a semiconductor device having reduced contact resistanceATOMERA INC·Filed 2018·Granted Mar 17, 2020·51 cites·21 claims
- 0299US10580866B1Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·21 claims
- 0399US10090395B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2018·Granted Oct 2, 2018·18 cites·30 claims
- 0499US9461167B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2016·Granted Oct 4, 2016·18 cites·16 claims
- 0599US9209261B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2015·Granted Dec 8, 2015·22 cites·30 claims
- 0698US11664427B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2022·Granted May 30, 2023·7 cites·32 claims
- 0798US11387325B2Vertical semiconductor device with enhanced contact structure and associated methodsATOMERA INC·Filed 2020·Granted Jul 12, 2022·12 cites·35 claims
- 0898US10879356B2Method for making a semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Dec 29, 2020·21 cites·26 claims
- 0998US10854717B2Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Dec 1, 2020·32 cites·20 claims
- 1098US10847618B2Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 24, 2020·33 cites·20 claims
- 1198US10840337B2Method for making a FINFET having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·21 claims
- 1298US10840336B2Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methodsATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·17 claims
- 1398US10840335B2Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·23 claims
- 1498US10818755B2Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Oct 27, 2020·33 cites·21 claims
- 1598US10777451B2Semiconductor device including enhanced contact structures having a superlatticeATOMERA INC·Filed 2019·Granted Sep 15, 2020·30 cites·27 claims
- 1698US10580867B1FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·22 claims
- 1798US9905691B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2016·Granted Feb 27, 2018·16 cites·30 claims
- 1897US7884003B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2008·Granted Feb 8, 2011·26 cites·7 claims
- 1997US7112478B2Insulated gate field effect transistor having passivated Schottky barriers to the channelACORN TECH INC·Filed 2004·Granted Sep 26, 2006·84 cites·13 claims
- 2097US6891234B1Transistor with workfunction-induced charge layerACORN TECH INC·Filed 2004·Granted May 10, 2005·199 cites·41 claims
- 2196US9425277B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsGRUPP DANIEL E·Filed 2012·Granted Aug 23, 2016·18 cites·18 claims
- 2296US7700416B1Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layerACORN TECH INC·Filed 2008·Granted Apr 20, 2010·53 cites·36 claims
- 2396US7462860B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2005·Granted Dec 9, 2008·23 cites·1 claims
- 2496US7084423B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2002·Granted Aug 1, 2006·62 cites·69 claims
- 2595US8916437B2Insulated gate field effect transistor having passivated schottky barriers to the channelACORN TECH INC·Filed 2013·Granted Dec 23, 2014·13 cites·2 claims
- 2695US8766336B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2012·Granted Jul 1, 2014·11 cites·84 claims
- 2795US8377767B2Insulated gate field effect transistor having passivated schottky barriers to the channelACORN TECH INC·Filed 2011·Granted Feb 19, 2013·14 cites·17 claims
- 2895US7883980B2Insulated gate field effect transistor having passivated schottky barriers to the channelACORN TECH INC·Filed 2006·Granted Feb 8, 2011·23 cites·12 claims
- 2994US8431469B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsGRUPP DANIEL E·Filed 2011·Granted Apr 30, 2013·11 cites·2 claims
- 3094US7851325B1Strained semiconductor using elastic edge relaxation, a buried stressor layer and a sacrificial stressor layerACORN TECH INC·Filed 2008·Granted Dec 14, 2010·23 cites·19 claims
- 3193US8263467B2Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistorGRUPP DANIEL E·Filed 2011·Granted Sep 11, 2012·18 cites·37 claims
- 3292US7176483B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2004·Granted Feb 13, 2007·66 cites·10 claims
- 3391US6833556B2Insulated gate field effect transistor having passivated schottky barriers to the channelACORN TECH INC·Filed 2003·Granted Dec 21, 2004·36 cites·32 claims
- 3489US10388748B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2017·Granted Aug 20, 2019·2 cites·14 claims
- 3589US8658523B2Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)FAULKNER CARL M·Filed 2010·Granted Feb 25, 2014·16 cites·4 claims
- 3688US9812542B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2016·Granted Nov 7, 2017·2 cites·18 claims
- 3788US7816240B2Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)ACORN TECH INC·Filed 2007·Granted Oct 19, 2010·14 cites·2 claims
- 3887US7972916B1Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recessesACORN TECH INC·Filed 2008·Granted Jul 5, 2011·14 cites·26 claims
- 3985US10950707B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN SEMI LLC·Filed 2020·Granted Mar 16, 2021·1 cites·23 claims
- 4085US8212336B2Field effect transistor source or drain with a multi-facet surfaceGOEBEL ANDREAS·Filed 2009·Granted Jul 3, 2012·21 cites·32 claims
- 4183US9583614B2Insulated gate field effect transistor having passivated schottky barriers to the channelACORN TECH INC·Filed 2014·Granted Feb 28, 2017·3 cites·4 claims
- 4283US7902029B2Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistorACORN TECH INC·Filed 2005·Granted Mar 8, 2011·10 cites·20 claims
- 4383US7382021B2Insulated gate field-effect transistor having III-VI source/drain layer(s)ACORN TECH INC·Filed 2004·Granted Jun 3, 2008·32 cites·19 claims
- 4480US8003486B2Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layerACORN TECH INC·Filed 2010·Granted Aug 23, 2011·4 cites·13 claims
- 4579US11355613B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN SEMI LLC·Filed 2021·Granted Jun 7, 2022·0 cites·11 claims
- 4676US11018237B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN SEMI LLC·Filed 2020·Granted May 25, 2021·0 cites·12 claims
- 4776US10937880B2Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN SEMI LLC·Filed 2020·Granted Mar 2, 2021·0 cites·28 claims
- 4874US11056569B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN SEMI LLC·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 4971US10186592B2Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctionsACORN TECH INC·Filed 2018·Granted Jan 22, 2019·0 cites·20 claims
- 5070US2025248090A1Method for making semiconductor device including superlattice source/drainATOMERA INC·Filed 2025·Application pending·0 cites
Showing the top 50 of 57 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →