Inventor · disambiguated record
Douglas M. Trickett
Also filed as: TRICKETT DOUGLAS · TRICKETT DOUGLAS M
17 granted patents·3 pending applications·735 citations·filing 2003–2019
94Inventor score
Top patents by PatentIndex Score
20 records- 0197US6875477B2Method for coating internal surface of plasma processing chamberHITACHI HIGH TECH CORP·Filed 2003·Granted Apr 5, 2005·411 cites·7 claims
- 0296US9373582B1Self aligned via in integrated circuitIBM·Filed 2015·Granted Jun 21, 2016·18 cites·8 claims
- 0396US8476165B2Method for thinning a bonding waferTRICKETT DOUGLAS M·Filed 2010·Granted Jul 2, 2013·223 cites·20 claims
- 0495US9613862B2Chamferless via structuresIBM·Filed 2015·Granted Apr 4, 2017·14 cites·19 claims
- 0595US9373543B1Forming interconnect features with reduced sidewall taperingGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 21, 2016·19 cites·20 claims
- 0694US9385078B1Self aligned via in integrated circuitIBM·Filed 2016·Granted Jul 5, 2016·11 cites·1 claims
- 0790US7279427B2Damage-free ashing process and system for post low-k etchTOKYO ELECTRON LTD·Filed 2005·Granted Oct 9, 2007·18 cites·12 claims
- 0888US10032668B2Chamferless via structuresIBM·Filed 2017·Granted Jul 24, 2018·4 cites·18 claims
- 0978US8202803B2Method to remove capping layer of insulation dielectric in interconnect structuresFEURPRIER YANNICK·Filed 2009·Granted Jun 19, 2012·7 cites·16 claims
- 1075US10388565B2Chamferless via structuresIBM·Filed 2018·Granted Aug 20, 2019·1 cites·18 claims
- 1175US9252051B1Method for top oxide rounding with protection of patterned featuresIBM·Filed 2014·Granted Feb 2, 2016·3 cites·20 claims
- 1273US9799559B1Methods employing sacrificial barrier layer for protection of vias during trench formationGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 24, 2017·2 cites·20 claims
- 1367US9768113B2Self aligned via in integrated circuitIBM·Filed 2016·Granted Sep 19, 2017·1 cites·11 claims
- 1465US7772110B2Electrical contacts for integrated circuits and methods of forming using gas cluster ion beam processingTOKYO ELECTRON LTD·Filed 2007·Granted Aug 10, 2010·3 cites·9 claims
- 1563US10937694B2Chamferless via structuresIBM·Filed 2019·Granted Mar 2, 2021·0 cites·20 claims
- 1663US10903118B2Chamferless via structuresIBM·Filed 2019·Granted Jan 26, 2021·0 cites·19 claims
- 1755US10957588B2Chamferless via structuresIBM·Filed 2016·Granted Mar 23, 2021·0 cites·20 claims
- 1845US2005084617A1Method for coating internal surface of plasma processing chamberFiled 2004·Application pending·0 cites
- 1940US2005112289A1Method for coating internal surface of plasma processing chamberFiled 2004·Application pending·0 cites
- 2036US2012064713A1Ultra-low-k dual damascene structure and method of fabricatingRUSSELL NOEL·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →