Inventor · disambiguated record
Gen P. Lauer
Also filed as: LAUER GEN P · LAUER GEN PEI
48 granted patents·2 pending applications·269 citations·filing 2011–2018
98Inventor score
Top patents by PatentIndex Score
50 records- 0199US9450180B1Structure and method to reduce shorting in STT-MRAM deviceIBM·Filed 2015·Granted Sep 20, 2016·65 cites·14 claims
- 0298US9705071B2Structure and method to reduce shorting and process degradation in STT-MRAM devicesIBM·Filed 2015·Granted Jul 11, 2017·19 cites·8 claims
- 0398US9502640B1Structure and method to reduce shorting in STT-MRAM deviceIBM·Filed 2015·Granted Nov 22, 2016·25 cites·6 claims
- 0496US9397287B1Magnetic tunnel junction with post-deposition hydrogenationIBM·Filed 2015·Granted Jul 19, 2016·16 cites·20 claims
- 0595US9705077B2Spin torque MRAM fabrication using negative tone lithography and ion beam etchingIBM·Filed 2015·Granted Jul 11, 2017·7 cites·16 claims
- 0695US9209095B2III-V, Ge, or SiGe fin base lateral bipolar transistor structure and methodIBM·Filed 2014·Granted Dec 8, 2015·18 cites·18 claims
- 0794US10243138B2Structure and method to reduce shorting and process degradation in STT-MRAM devicesIBM·Filed 2018·Granted Mar 26, 2019·7 cites·10 claims
- 0894US9660179B1Enhanced coercivity in MTJ devices by contact depth controlIBM·Filed 2015·Granted May 23, 2017·13 cites·6 claims
- 0994US9515252B1Low degradation MRAM encapsulation process using silicon-rich silicon nitride filmIBM·Filed 2015·Granted Dec 6, 2016·13 cites·20 claims
- 1094US9391163B2Stacked planar double-gate lamellar field-effect transistorIBM·Filed 2014·Granted Jul 12, 2016·11 cites·1 claims
- 1193US9812370B2III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technologyIBM·Filed 2016·Granted Nov 7, 2017·7 cites·10 claims
- 1293US9653679B1Magnetoresistive structures with stressed layerIBM·Filed 2016·Granted May 16, 2017·8 cites·18 claims
- 1391US9601686B1Magnetoresistive structures with stressed layerIBM·Filed 2015·Granted Mar 21, 2017·7 cites·4 claims
- 1490US9373638B1Complementary metal-oxide silicon having silicon and silicon germanium channelsIBM·Filed 2015·Granted Jun 21, 2016·5 cites·12 claims
- 1587US10256397B2Structure and method to reduce shorting and process degradation in stt-MRAM devicesIBM·Filed 2018·Granted Apr 9, 2019·3 cites·14 claims
- 1687US8618636B1Fin bipolar transistors having self-aligned collector and emitter regionsCHANG JOSEPHINE B·Filed 2012·Granted Dec 31, 2013·7 cites·18 claims
- 1786US9960347B2Structure and method to reduce shorting and process degradation in STT-MRAM devicesIBM·Filed 2017·Granted May 1, 2018·3 cites·10 claims
- 1885US10170609B2Internal spacer formation from selective oxidation for Fin-first wire-last replacement gate-all-around nanowire FETIBM·Filed 2015·Granted Jan 1, 2019·4 cites·11 claims
- 1985US9496184B2III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technologyIBM·Filed 2014·Granted Nov 15, 2016·5 cites·9 claims
- 2082US9673386B2Structure and method to reduce shorting in STT-MRAM deviceIBM·Filed 2016·Granted Jun 6, 2017·2 cites·20 claims
- 2180US9105650B2Lateral bipolar transistor and CMOS hybrid technologyIBM·Filed 2014·Granted Aug 11, 2015·4 cites·12 claims
- 2277US8614117B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorBRIGHTSKY MATTHEW J·Filed 2012·Granted Dec 24, 2013·4 cites·15 claims
- 2376US10170608B2Internal spacer formation from selective oxidation for fin-first wire-last replacement gate-all-around nanowire FETIBM·Filed 2015·Granted Jan 1, 2019·2 cites·12 claims
- 2476US9947863B2Structure and method to reduce shorting in STT-MRAM deviceIBM·Filed 2017·Granted Apr 17, 2018·1 cites·20 claims
- 2575US9853210B2Reduced process degradation of spin torque magnetoresistive random access memoryIBM·Filed 2015·Granted Dec 26, 2017·2 cites·9 claims
- 2675US8617957B1Fin bipolar transistors having self-aligned collector and emitter regionsCHANG JOSEPHINE B·Filed 2012·Granted Dec 31, 2013·3 cites·16 claims
- 2773US9543388B2Complementary metal-oxide silicon having silicon and silicon germanium channelsIBM·Filed 2016·Granted Jan 10, 2017·1 cites·6 claims
- 2869US8610181B2V-groove source/drain MOSFET and process for fabricating sameGUILLORN MICHAEL A·Filed 2012·Granted Dec 17, 2013·2 cites·15 claims
- 2969US8603868B2V-groove source/drain MOSFET and process for fabricating sameGUILLORN MICHAEL A·Filed 2011·Granted Dec 10, 2013·2 cites·12 claims
- 3067US9691972B1Low temperature encapsulation for magnetic tunnel junctionIBM·Filed 2015·Granted Jun 27, 2017·1 cites·20 claims
- 3166US10084127B2Enhanced coercivity in MTJ devices by contact depth controlIBM·Filed 2017·Granted Sep 25, 2018·1 cites·6 claims
- 3262US10388857B2Spin torque MRAM fabrication using negative tone lithography and ion beam etchingIBM·Filed 2016·Granted Aug 20, 2019·1 cites·8 claims
- 3360US8853662B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorIBM·Filed 2013·Granted Oct 7, 2014·0 cites·8 claims
- 3458US9954063B2Stacked planar double-gate lamellar field-effect transistorIBM·Filed 2016·Granted Apr 24, 2018·0 cites·18 claims
- 3558US9954062B2Stacked planar double-gate lamellar field-effect transistorIBM·Filed 2016·Granted Apr 24, 2018·0 cites·1 claims
- 3658US9859375B2Stacked planar double-gate lamellar field-effect transistorIBM·Filed 2016·Granted Jan 2, 2018·0 cites·7 claims
- 3758US9748310B2Structure and method to reduce shorting in STT-MRAM deviceIBM·Filed 2016·Granted Aug 29, 2017·0 cites·19 claims
- 3856US9466673B2Complementary metal-oxide silicon having silicon and silicon germanium channelsIBM·Filed 2016·Granted Oct 11, 2016·0 cites·10 claims
- 3954US9240324B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 19, 2016·0 cites·10 claims
- 4054US8592250B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorBRIGHTSKY MATTHEW J·Filed 2012·Granted Nov 26, 2013·0 cites·20 claims
- 4153US10497862B2Enhanced coercivity in MTJ devices by contact depth controlIBM·Filed 2018·Granted Dec 3, 2019·0 cites·20 claims
- 4251US8927431B2High-rate chemical vapor etch of silicon substratesIBM·Filed 2013·Granted Jan 6, 2015·0 cites·20 claims
- 4351US8673717B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorBRIGHTSKY MATTHEW J·Filed 2012·Granted Mar 18, 2014·0 cites·11 claims
- 4450US11011698B2Enhanced coercivity in MTJ devices by contact depth controlIBM·Filed 2017·Granted May 18, 2021·0 cites·11 claims
- 4550US9012970B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorBRIGHTSKY MATTHEW J·Filed 2012·Granted Apr 21, 2015·0 cites·10 claims
- 4649US10170698B2Spin torque MRAM fabrication using negative tone lithography and ion beam etchingIBM·Filed 2017·Granted Jan 1, 2019·0 cites·17 claims
- 4749US8835898B2Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistorBRIGHTSKY MATTHEW J·Filed 2012·Granted Sep 16, 2014·0 cites·6 claims
- 4848US2014073106A1Lateral bipolar transistor and cmos hybrid technologyCHANG JOSEPHINE B·Filed 2012·Application pending·0 cites
- 4943US9209086B2Low temperature salicide for replacement gate nanowiresGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 8, 2015·0 cites·11 claims
- 5036US2017186944A1Enhancement of spin transfer torque magnetoresistive random access memory device using hydrogen plasmaIBM·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →